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參數(shù)資料
| 型號： | DSPE56007FJ66 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 23/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ66 |
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Signal/Connection Descriptions
On-Chip Emulation (OnCE
TM
) Port
MOTOROLA
DSP56007/D
1-17
DSCK
OS1
Input
Output
Output,
Driven Low
Debug Serial Clock (DSCK)
—The DSCK/ OS1 signal,
when an input, is the signal through which the serial clock
is supplied to the OnCE port. The serial clock provides
pulses required to shift data into and out of the OnCE port.
Data is clocked into the OnCE port on the falling edge and
is clocked out of the OnCE port on the rising edge.
Operating Status 1 (OS1)
—If the OS1 signal is an output
and used in conjunction with the OS0 signal, it provides
information about the DSP status when the DSP is not in the
Debug mode. The debug serial clock frequency must be no
greater than 1/ 8 of the processor clock frequency. The
signal is tri-stated when it is changing from input to output.
Note:
If the OnCE port is in use, an external pull-down resistor
should be attached to the DSCK/ OS1 pin. If the OnCE
port is not in use, the resistor is not required.
DSO
Output
Driven High
Debug Serial Output (DSO)
—The DSO line provides the
data contained in one of the OnCE port controller registers
as specified by the last command received from the
command controller. The Most Significant Bit (MSB) of the
data word is always shifted out of the OnCE port first. Data
is clocked out of the OnCE port on the rising edge of DSCK.
The DSO line also provides acknowledge pulses to the
external command controller. When the DSP enters the
Debug mode, the DSO line will be pulsed low to indicate
that the OnCE port is waiting for commands. After
receiving a read command, the DSO line will be pulsed low
to indicate that the requested data is available and the
OnCE port is ready to receive clock pulses in order to
deliver the data. After receiving a write command, the DSO
line will be pulsed low to indicate that the OnCE port is
ready to receive the data to be written; after the data is
written, another acknowledge pulse will be provided.
Note:
During hardware reset and when idle, the DSO line is
held high.
Table 1-12
On-Chip Emulation Port Signals (Continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
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