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參數(shù)資料
| 型號： | DSP56F826BU80 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/56頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | EBI/EMI，SCI，SPI，SSI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 46 |
| 程序存儲器容量： | 67KB（33.5K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4.5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.25 V ~ 2.75 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor
17
IRQA
32
Input
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will exit
the Stop state.
IRQB
33
Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET
45
Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the device is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
EXTBOOT
25
Input
(Schmitt)
External Boot—This input is tied to VDD to force device to boot from off-chip
memory. Otherwise, it is tied to ground.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
Pin No.
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F826BU80E | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V |
| DSP56F826D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor |
| DSP56F826E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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