參數(shù)資料
型號(hào)： DSP56F801FA80E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 375K
代理商： DSP56F801FA80E
Interrupt and Program Control Signals
56F801 Technical Data, Rev. 16
Freescale Semiconductor
11
2.4 Interrupt and Program Control Signals
2.5 Pulse Width Modulator (PWM) Signals
1
XTAL
GPIOB3
Output
Input/
Output
Chip-
driven
Input
Crystal Oscillator Output
—This output should be connected to an 8MHz
external crystal or ceramic resonator. For more information, please refer to
Section 3.5
.
This pin can also be connected to an external clock source. For more
information, please refer to
Section 3.5.3
.
Port B GPIO
—This multiplexed pin is a General Purpose I/O (GPIO) pin that
can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the XTAL pin is not needed.
Table 2-6 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State
During Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered.
1
RESET
Input
(Schmitt)
Input
Reset
—This input is a direct hardware reset on the processor. When
RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
Table 2-7 Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0-5
Output
Tri-stated
PWMA0-5
— These are six PWMA output pins.
1
FAULTA0
Input
(Schmitt)
Input
FAULTA0
— This fault input pin is used for disabling selected PWMA
outputs in cases where fault conditions originate off-chip.
Table 2-5 PLL and Clock (Continued)
No. of
Pins
Signal
Name
Signal
Type
State
During Reset
Signal Description
相關(guān)PDF資料
PDF描述
DSP56F801 16-bit Hybrid Controller(16位混合控制器)
DSP56F803E 16-bit Digital Signal Controllers
DSP56F805E 16-bit Digital Signal Controllers
DSP56F805FV80E 16-bit Digital Signal Controllers
DSP56F805 16-bit Hybrid Controller(16位混合控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F801FA80E 制造商:Freescale Semiconductor 功能描述:IC
DSP56F801PB 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-bit Digital Signal Processor
DSP56F802 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F802PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F802 16-Bit Hybrid Controller Product Brief
DSP56F802TA60 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 60Mhz/30MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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