
Serial Host Interface (SHI) I
2
C Protocol Timing
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
3-43
175 SCL low period
T
LOW
4.7
—
1.3
—
μ
s
176 SCL high period
T
HIGH
4.0
—
1.3
—
μ
s
177 SCL and SDA rise time
T
R
—
1000
20 + 0.1
×
C
b
300
ns
178 SCL and SDA fall time
T
F
—
300
20 + 0.1
×
C
b
300
ns
179 Data set-up time
T
SU;DAT
250
—
100
—
ns
180 Data hold time
T
HD;DAT
0.0
—
0.0
0.9
μ
s
181 DSP clock frequency
Filters bypassed
Narrow filters enabled
Wide filters enabled
F
DSP
10.6
11.8
13.1
—
—
—
28.5
39.7
61.0
—
—
—
MHz
182 SCL low to data out valid
T
VD;DAT
—
3.4
—
0.9
μ
s
183 Stop condition setup time
T
SU;STO
4.0
—
0.6
—
μ
s
184 HREQ in deassertion to last SCL edge (HREQ in set-up
time)
t
SU;RQI
0.0
—
0.0
—
ns
186 First SCL sampling edge to HREQ output deassertion
2
Filters bypassed
Narrow filters enabled
Wide filters enabled
T
NG;RQO
2
×
T
C
+ 30
2
×
T
C
+ 120
2
×
T
C
+ 208
—
—
—
50
140
228
—
—
—
50
140
228
ns
187 Last SCL edge to HREQ output not deasserted
2
Filters bypassed
Narrow filters enabled
Wide filters enabled
T
AS;RQO
2
×
T
C
+ 30
2
×
T
C
+ 80
2
×
T
C
+ 135
50
100
155
—
—
—
50
100
155
—
—
—
ns
188 HREQ in assertion to first SCL edge
Filters bypassed
Narrow filters enabled
Wide filters enabled
T
AS;RQI
0.5
×
T
I
2
CCP
-
0.5
×
T
C
- 21
4327
4282
4238
—
—
—
927
882
838
—
—
—
ns
187 First SCL edge to HREQ in not asserted (HREQ in hold
time.)
t
HO;RQI
0.0
—
0.0
—
ns
1
V
CC
= 1.8 V ± 5%; T
J
= –40°C to +95°C, C
L
= 50 pF
2
Pull-up resistor: R
P (min)
= 1.5 kOhm
3
Capacitive load: C
b (max)
= 400 pF
4
It is recommended to enable the wide filters when operating in the I
2
C Standard Mode.
5
The timing values are derived from frequencies not exceeding 100 MHz.
6
It is recommended to enable the narrow filters when operating in the I
2
C Fast Mode.
Table 3-17 SHI I
2
C Protocol Timing (continued)
Standard I
2
C
No.
Characteristics
1, 2, 3
Symbol/
Expression
Standard
4, 5
Fast-Mode
5, 6
Unit
Min
Max
Min
Max