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參數(shù)資料
| 型號： | DSP56301AG80B1 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 80MHZ GP 208-LQFP |
| 產(chǎn)品變化通告： | DSP56301 Discontinuation 12/Nov/2009 |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時(shí)鐘速率： | 80MHz |
| 非易失內(nèi)存： | ROM（9 kB） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-LQFP |
| 供應(yīng)商設(shè)備封裝： | 208-LQFP |
| 包裝： | 托盤 |
DSP56301 Product Brief, Rev. 2
2
Freescale Semiconductor
DSP56301 Features
High-performance DSP56300 core
— 66/80/100 Million Instructions Per Second (MIPS) with a 66/80/100 MHz clock at 3.3 V
— Object code compatible with the DSP56000 core
— Highly parallel instruction set
— Fully pipelined 24 x 24-bit parallel multiplier-accumulator
— 56-bit parallel barrel shifter
— 24-bit or 16-bit arithmetic support under software control
— Position independent code support
— Addressing modes optimized for DSP applications
— On-chip instruction cache controller
— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
— On-chip concurrent six-channel DMA controller
— On-chip Phase Lock Loop (PLL) and clock generator
— On-Chip Emulation (OnCE) module
— Joint Action Test Group (JTAG) Test Access Port (TAP)
— Address tracing mode that reflects internal accesses at the external port
On-chip memories
— Program RAM, Instruction Cache, X data RAM, and Y data RAM size are programmable:
—192
× 24-bit bootstrap ROM
Off-chip memory expansion
— Data memory expansion to two 16 M x 24-bit word memory spaces
— Program memory expansion to one 16 M x 24-bit word memory space
— External memory expansion port
— Chip Select Logic requiring no additional circuitry to interface to SRAMs and SSRAMs
— On-chip DRAM controller that requires no additional circuitry to interface to DRAMs
On-chip peripherals
— 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with no additional interface logic
required for other DSP563xx buses
— ISA interface requires only 74LS45-style buffer
— Two Enhanced Synchronous Serial Interfaces (ESSI)
— Serial Communications Interface (SCI) with baud rate generator
— Triple timer module
— Up to 42 programmable General Purpose I/O pins (GPIO), depending on which peripherals are enabled
Reduced power dissipation
— Very low power CMOS design
— Wait and Stop low power standby modes
— Fully-static logic, operation frequency down to 0 Hz (DC)
— Optimized power management circuitry
Instruction
Cache
Switch
Mode
Program
RAM Size
Instruction
Cache Size
X Data RAM
Size
Y Data Ram
Size
disabled
4096
× 24-bit
0
2048
× 24-bit
2048
× 24-bit
enabled
disabled
3072
× 24-bit
1024
× 24-bit
2048
× 24-bit
2048
× 24-bit
disabled
enabled
2048
× 24-bit
0
3072
× 24-bit
3072
× 24-bit
enabled
1024
× 24-bit
1024
× 24-bit
3072
× 24-bit
3072
× 24-bit
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