參數(shù)資料
型號(hào)： DSD1792ADBRG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 15/57頁(yè)
文件大?。?/td> 0K
描述： IC DAC 24BIT SER 28-SSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 24
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 335mW
工作溫度： -25°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 4 電流，單極
采樣率（每秒）： 200k
DSD1792
SLES067B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
22
Register Map
The mode control register map is shown in Table 3. Registers 16–21 include an R/W bit, which determines whether a
register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only.
Table 3. Mode Control Register Map
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
1
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
1
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
Register 18
R/W
0
1
0
1
0
ATLD
FMT2
FMT1
FMT0
DMF1
DMF0
DME
MUTE
Register 19
R/W
0
1
0
1
REV
ATS1
ATS0
OPE
ZOE
DFMS
FLT
INZD
Register 20
R/W
0
1
0
1
0
RSV
SRST
DSD
DFTH
MONO
CHSL
OS1
OS0
Register 21
R/W
0
1
0
1
0
1
RSV
DZ1
DZ0
PCMZ
Register 22
R
0
1
0
1
0
RSV
ZFGR
ZFGL
Register 23
R
0
1
0
1
RSV
ID4
ID3
ID2
ID1
ID0
Register Definitions
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
0
1
0
ATL7
ATL6
ATL5
ATL4
ATL3
ATL2
ATL1
ATL0
Register 17
R/W
0
1
0
1
ATR7
ATR6
ATR5
ATR4
ATR3
ATR2
ATR1
ATR0
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
ATx[7:0]: Digital Attenuation Level Setting
These bits are available for read and write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB steps.
Alternatively, the attenuator can be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control register
18) is common to both attenuators. ATLD must be set to 1 in order to change an attenuator setting. The attenuation level
can be set using the following formula:
Attenuation level (dB) = 0.5 dB
(ATx[7:0]DEC – 255)
where ATx[7:0]DEC = 0 through 255
For ATx[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. The following table shows attenuation levels
for various settings:
ATx[7:0]
Decimal Value
Attenuation Level Setting
1111 1111b
255
0 dB, no attenuation (default)
1111 1110b
254
–0.5 dB
1111 1101b
253
–1.0 dB
L
LL
0001 0000b
16
–119.5 dB
0000 1111b
15
–120.0 dB
0000 1110b
14
Mute
L
LL
0000 0000b
0
Mute
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DSD1792DBG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24-Bit 192kHz Smplng Adv Stg Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類(lèi)型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
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