參數(shù)資料
型號： DSD1702
英文描述： ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER
中文描述： 增強的多格式，Δ-Σ，音頻數(shù)字模擬轉換器
文件頁數(shù)： 11/28頁
文件大?。?/td> 417K
代理商： DSD1702
DSD1702
SLES005A
–
JUNE 2001
–
REVISED FEBRUARY 2002
11
www.ti.com
register write operation
All write operations for the serial control port use 16-bit data words. Figure 7 shows the control data word format.
The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or
address). The least significant eight bits, D[7:0], contain the data to be written to the register specified by
IDX[6:0].
Figure 8 shows the functional timing diagram for the serial control port. MS is held at a logic 1 state until a register
needs to be written. To start the register write cycle, MS is set to logic
0. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed,
the data is latched into the indexed mode control register. To write the next data, MS must be set to 1 once
.
control interface timing requirements
Figure 9 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
Register Index (or Address)
MSB
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1
D7
IDX0
D6
D5
D4
D3
D2
D1
D0
LSB
Register Data
Figure 7. Control Data Word Format MD
0
IDX6
D7
D6
D5
D4
D3
D2
D1
D0
X
IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
X
X
0
IDX6
MS
MC
MD
Figure 8. Register Write Operation
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