參數(shù)資料
型號: DS9034PCX
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Timer or RTC
英文描述: 0 TIMER(S), REAL TIME CLOCK, DMA34
封裝: POWERCAP MODULE-34
文件頁數(shù): 13/16頁
文件大?。?/td> 190K
代理商: DS9034PCX
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
6 of 16
CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within
1 minute per month at +25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the
RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within
1.53 minutes per month (35ppm) at +25°C. The
electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, please refer to Application
Note 58: Crystal Considerations with Dallas Real-Time Clocks.
Table 2. Register Map
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION
RANGE
1FFF
10 Year
Year
00–99
1FFE
X
10
Month
01–12
1FFD
X
10 Date
Date
01–31
1FFC
BF
FT
X
Day
01–07
1FFB
X
10 Hour
Hour
00–23
1FFA
X
10 Minutes
Minutes
00–59
1FF9
OSC
10 Seconds
Seconds
00–59
1FF8
W
R
10 Century
Century
Control
00–39
OSC = STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = SEE NOTE BELOW
BF = BATTERY FLAG
Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever
OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in
the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable,
providing that the,
CE and OE access times and states are satisfied. If CE, or OE access times and states
are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access
time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are
activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are
changed while
CE and OE remain valid, output data will remain valid for output data hold time (t
OH) but
will then go indeterminate until the next address access.
相關(guān)PDF資料
PDF描述
DS1743-100 0 TIMER(S), REAL TIME CLOCK, DMA28
DS1743WP-120 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1743WP-150 0 TIMER(S), REAL TIME CLOCK, DMA34
DS1743W-150 0 TIMER(S), REAL TIME CLOCK, DMA28
DS1743P-100 0 TIMER(S), REAL TIME CLOCK, DMA34
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