參數(shù)資料
型號： DS89C21TMX
元件分類： 收發(fā)器
英文描述： Transceiver
中文描述： 收發(fā)器
文件頁數(shù)： 12/48頁
文件大?。?/td> 934K
代理商： DS89C21TMX
DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
12 of 48
PIN DESCRIPTION
PIN
PDIP
PLCC
TQFP
NAME
FUNCTION
40
12, 44
6, 38
V
CC
+5V
20
1, 22, 23,
34
16, 17, 28,
39
GND
Logic Ground
9
10
4
RST
External Reset.
The RST input pin is bidirectional and contains a Schmitt Trigger to
recognize external active-high reset inputs. The pin also employs an internal pulldown
resistor to allow for a combination of wire-ORed external reset sources. An RC is not
required for power-up, as the device provides this function internally.
19
21
15
XTAL1
18
20
14
XTAL2
Crystal Oscillators.
These pins provide support for fundamental-mode parallel-resonant
AT-cut crystals. XTAL1 also acts as an input if there is an external clock source in place of
a crystal. XTAL2 serves as the output of the crystal amplifier.
29
32
26
PSEN
Program Store Enable.
This signal is commonly connected to optional external program
memory as a chip enable.
PSEN
provides an active-low pulse and is driven high when
external program memory is not being accessed. In one-cycle page mode 1,
PSEN
remains low for consecutive page hits.
Address Latch Enable.
This signal functions as a clock to latch the external address LSB
from the multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373-family transparent latch. In default mode, ALE has a pulse
width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE
pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE
is high when using the EMI reduction mode and during a reset condition. ALE can be
enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON
during external memory accesses. As an alternate mode, this pin (
PROG
) is used to
execute the parallel program function.
30
33
27
ALE/
PROG
39
43
37
P0.0 (AD0)
38
42
36
P0.1 (AD1)
37
41
35
P0.2 (AD2)
36
40
34
P0.3 (AD3)
35
39
33
P0.4 (AD4)
34
38
32
P0.5 (AD5)
33
37
31
P0.6 (AD6)
32
36
30
P0.7 (AD7)
Port 0 (AD0–AD7), I/O.
Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an
alternate function, Port 0 can function as the multiplexed address/data bus to access off-
chip memory. During the time when ALE is high, the LSB of a memory address is
presented. When ALE falls to logic 0, the port transitions to a bidirectional data bus. This
bus is used to read external program memory and read/write external RAM or peripherals.
When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset
condition of port 0 is tri-state. Pullup resistors are required only when using port 0 as an
I/O port.
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參數(shù)描述
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DS89C386TMEA 功能描述:總線接收器 RoHS:否 制造商:Texas Instruments 接收機數(shù)量:4 接收機信號類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel
DS89C386TMEA/NOPB 功能描述:總線接收器 RoHS:否 制造商:Texas Instruments 接收機數(shù)量:4 接收機信號類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel
DS89C386TMEAX 制造商:Texas Instruments 功能描述:Twelve Receiver RS-422 48-Pin SSOP T/R
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