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參數(shù)資料
| 型號(hào)： | DS87C550 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | EPROM High-Speed Micro with A/D and PWM(帶 A/D 和 PWM的EPROM/ROM高速微控制器) |
| 中文描述： | 存儲(chǔ)器高速微與A / D及PWM（帶A / D轉(zhuǎn)換和脈寬調(diào)制的存儲(chǔ)器/ ROM的高速微控制器） |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 119K |
| 代理商： | DS87C550 |
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APPLICATION NOTE 78
030998 8/27
One exception to the above timing relationship is that
serial port switchbacks will occur immediately upon
receipt of a falling edge on an enabled serial port
receiver. The switchback will occur at the start of the
next internal clock cycle following the falling edge. Fig-
ure 4 demonstrates the timing relationship between
serial port activity and switchbacks.
SERIAL PORT DRIVEN SWITCHBACK
Figure 4
C1
C2
C3
C4
C1
C2
C3 C4 C1 C2C3 C4 C1 C2
MACHINE CYCLE 1
MACHINE CYCLE 2
PMM1 OR PMM2
OP FULL
CYCLE 3
INTERNAL
CLOCK
ALE
RX
SPRA0,
SERIAL START BIT
NOTES:
1. Internal Cx cycle is 16 external clock cycles for PMM1 and 256 external clock cycles for PMM2.
2. SPRA0 and SPRA1 will change within 1 machine cycle of the falling edge RX.
3. Example shows single–cycle instructions. Execution of the interrupt and switchback will occur at the end of
the last machine cycle of the instruction in which the interrupt is acknowledged.
Interrupt Priority
Because the switchback feature uses interrupts to qual-
ify execution, it is affected by interrupt priorities. The
external interrupts initiate a switchback upon the start of
the interrupt service routine. If a higher priority interrupt
is in progress, the associated switchback will remain
pending. It is not possible to enable or disable the
switchback function for individual interrupt sources,
except by enabling or disabling the specific interrupt.
The following example will illustrate how a problem
could occur if the priority of the interrupt sources is not
taken into account. Assume that the user is employing
both Timer 0 and External Interrupt 1 in a design which
utilizes PMM. While operating in PMM, a Timer 0 inter-
rupt occurs, and the device begins executing the inter-
rupt service routine (ISR). During the Timer 0 ISR, an
External Interrupt 1 occurs, signaling an external event
that needs to be serviced quickly. Because both inter-
rupts have the same priority, External Interrupt 1 will
remain pending until completion of the Timer 0 ISR.
Although such interrupt priorities are a normal consider-
ation in any design, the reduced operating speed in
PMM will further increase the latency associated with
servicing External Interrupt 1. This could be avoided by
specifying External Interrupt 1 as a high priority interrupt
and leaving Timer 0 as a low priority interrupt.
A serial port–initiated switchback does not utilize the
interrupt structure, and is therefore not affected by inter-
rupt priorities. Serial port–initiated switchbacks are
enabled or disabled via the specific receiver enable bit
(SCON0.4 or SCON1.4). The ability of a serial port to ini-
tiate a switchback is not dependent on the Enable Serial
Port Interrupt bits (IE.4 or IE.6).
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| DS87C550-FCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-FNL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-KCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-QCL | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM |
| DS87C550-QCL+ | 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設(shè)備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件 |
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