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參數(shù)資料
| 型號： | DS80CH11 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Microcontroller |
| 英文描述： | 8-BIT, MICROCONTROLLER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 53/88頁 |
| 文件大?。?/td> | 598K |
| 代理商： | DS80CH11 |
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DS80CH11
011200 57/88
PMDIN1; SFR ADDR.=0BEH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMDIN2; SFR ADDR.=0F6H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Read/Write Access: Read only.
Initialization: Undefined on any type of reset
Each input data register (KBDIN, PMDIN1 or PMDIN2)
is a read–only register to the SEM and a write–only reg-
ister to the host. The associated input buffer full flag
(KIBF, PIBF1 or PIBF2) will be set when the host CPU
writes to one of the input buffers. The SEM can enable
an “input buffer full” interrupt on any port by setting the
associated interrupt enable bit (EKB, EPB1 or EPB2).
Upon interrupt, the SEM’s firmware should check to see
if the incoming byte is a command or data by reading the
command/data flag, i.e., KC/D, PC/D1 or PC/D2, in the
status register followed by a read of the input data regis-
ter. The contents of the input data registers are unaf-
fected by any type of reset.
9.4
KBSTAT / PMSTAT1/PMSTAT2 – STATUS REGISTERS
KBSTAT; SFR ADDR.=0ADH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
KST7
KST6
KST5
KST4
KC/D
KST2
KIBF
KOBF
PMSTAT1; SFR ADDR.=0BDH
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P1ST7
P1ST6
P1ST5
P1ST4
PC/D1
P1ST2
PIBF1
POBF1
PMSTAT2; SFR ADDR.=0F5H
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P2ST7
P2ST6
P2ST5
P2ST4
PC/D2
P2ST2
PIBF2
POBF2
Read/Write Access: Unrestricted.
Initialization: XXXXXX00B on any type of reset
The operation of the bits in the status registers of both
ports are summarized below:
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