參數(shù)資料
型號: DS80C390-QNR
元件分類: 微處理器
英文描述: Dual CAN High-Speed Microprocessor
中文描述: 雙CAN高速微處理器
文件頁數(shù): 4/58頁
文件大小: 5486K
代理商: DS80C390-QNR
DS80C390
4 of 58
110199
PIN DESCRIPTION
Table 1
LQFP
PLCC
SIGNAL
NAME
V
CC
DESCRIPTION
8, 22,
40, 56
9, 25,
41, 57
46
17, 32,
51, 68
1, 18,
35, 52
57
+5V
GND
Digital Circuit Ground
ALE
Address Latch Enable
- Output. When the
MUX
pin is low, this
pin outputs a clock to latch the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external transparent latch. ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. When the
MUX
pin is high, the pin will toggle
continuously if the ALEOFF bit is cleared. ALE is forced high
when the device is in a Reset condition or if the ALEOFF bit is set
while the
MUX
pin is high.
Program Store Enable
- Output. This signal is the chip enable for
external ROM memory.
PSEN
provides an active low pulse and is
driven high when external ROM is not being accessed.
External Access Enable
- Input. This pin must be tied to GND for
proper operation.
Multiplex/Demultiplex Select
- Input. This pin selects if the
address/data
bus
operates
in
demultiplexed (
MUX
=1) mode.
Reset
- Input. The RST input pin contains a Schmitt voltage input
to recognize external active high Reset inputs. The pin also
employs an internal pulldown resistor to allow for a combination of
wired OR external Reset sources. An RC circuit is not required for
power-up, as the device provides this function internally.
Reset Output Low
- Output. This active low signal will be
asserted:
When the processor has entered reset via the RST pin,
During crystal warm-up period following power-on or Stop mode,
During a watchdog timer reset (2 cycles duration),
During an oscillator failure (if OFDE=1),
Whenever V
CC
V
RST
XTAL1, XTAL2
- Crystal oscillator pins support fundamental
mode, parallel resonant, AT cut crystals. XTAL1 is the input if an
external clock source is used in place of a crystal. XTAL2 is the
output of the crystal amplifier.
AD0-7 (Port 0)
- I/O. When the
MUX
pin is tied low, Port 0 is the
multiplexed address/data bus. While ALE is high, the LSB of a
memory address is presented. While ALE falls, the port transitions
to a bi-directional data bus. When the
MUX
pin is tied high, Port 0
functions as the bi-directional data bus. Port 0 cannot be modified
by software. The reset condition of Port 0 pins is high. No pullup
resistors are needed.
45
56
PSEN
47
58
EA
26
36
MUX
multiplexed
(
MUX
=0)
or
2
11
RST
3
12
RSTOL
23,
24
33,
34
XTAL2,
XTAL1
55
54
53
52
51
50
49
48
67
66
65
64
63
62
61
59
AD0 / D0
AD1 / D1
AD2 / D2
AD3 / D3
AD4 / D4
AD5 / D5
AD6 / D6
AD7 / D7
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相關代理商/技術參數(shù)
參數(shù)描述
DS80C390-QNR+ 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
DS80C400 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontroller
DS80C400_03 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontroller
DS80C400_07 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontroller
DS80C400_09 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontroller