
DS80C320/DS80C323 
14 of 42 
Timer 2.  CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user desires very 
fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent. 
POWER-FAIL RESET 
The DS80C320/DS80C323 incorporates a precision band-gap voltage reference to determine when V
CC
 is 
out of tolerance. While powering up, internal circuits will hold the device in a reset state until V
CC
 rises 
above the V
RST
 reset threshold. Once V
CC
 is above this level, the oscillator will begin running. An internal 
reset circuit will then count 65536 clocks to allow time for power and the oscillator to stabilize. The 
microcontroller will then exit the reset condition. No external components are needed to generate a power 
on reset. During power-down or during a severe power glitch, as V
CC
 falls below V
RST
, the 
microcontroller will also generate its own reset. It will hold the reset condition as long as power remains 
below the threshold. This reset will occur automatically, needing no action from the user or from the 
software. Refer to the Electrical Specifications for the exact value of V
RST
. 
POWER-FAIL INTERRUPT 
The same reference that generates a precision reset threshold can also generate an optional early warning 
Power-fail Interrupt (PFI). When enabled by the application software, this interrupt always has the 
highest priority. On detecting that the V
CC
 has dropped below V
PFW
 and that the PFI is enabled, the 
processor will vector to ROM address 0033h. The PFI enable is located in the Watchdog Control SFR 
(WDCON - D8h).  Setting WDCON.5 to a logic 1 will enable the PFI. The application software can also 
read a flag at WDCON.4.  This bit is set when a PFI condition has occurred. The flag is independent of 
the interrupt enable and software must manually clear it. 
WATCHDOG TIMER 
For applications that can not afford to run out of control, the DS80C320/DS80C323 incorporates a 
programmable watchdog timer circuit. It resets the microcontroller if software fails to reset the watchdog 
before the selected time interval has elapsed. The user selects one of four timeout values. After enabling 
the watchdog, software must reset the timer prior to expiration of the interval, or the CPU will be reset. 
Both the Watchdog Enable and the Watchdog Reset bits are protected by a “Timed Access” circuit. This 
prevents accidentally clearing the watchdog. Timeout values are precise since they are related to the 
crystal frequency as shown below in Table 4. For reference, the time periods at 25 MHz are also shown. 
The watchdog timer also provides a useful option for systems that may not require a reset. If enabled, 
then 512 clocks before giving a reset, the watchdog will give an interrupt. The interrupt can also serve as 
a convenient time-base generator, or be used to wake-up the processor from Idle mode. The watchdog 
function is controlled in the Clock Control (CKCON - 8Eh), Watchdog Control (WDCON - D8h), and 
Extended Interrupt Enable (EIE - E8h) SFRs. CKCON.7 and CKCON.6 are called WD1 and WD0 
respectively and are used to select the watchdog timeout period as shown in Table 4. 
WATCHDOG TIMEOUT VALUES 
Table 4 
INTERRUPT 
TIME 
RESET 
WD1 
WD0 
TIMEOUT 
(@25 MHz) 
TIMEOUT 
0
0 
2
17
 clocks 
5.243 ms 
2
17
 + 512 clocks 
0 
1 
2
20
 clocks 
41.94 ms 
2
20
 + 512 clocks 
1 
0 
2
23
 clocks 
335.54 ms 
2
23
 + 512 clocks 
1 
1 
2
26
 clocks 
2684.35 ms 
2
26
 + 512 clocks 
TIME 
(@25 MHz) 
5.263 ms 
j
41.96 ms 
335.56 ms 
2684.38 ms