The voltage supervisor monitors the VDD supply. A
參數(shù)資料
型號(hào)： DS8005-KIT#
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 2/20頁(yè)
文件大?。?/td> 0K
描述： EVALUATION KIT FOR DS8005
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： DS8005
已供物品： 板
相關(guān)產(chǎn)品： DS8005-RRX+-ND - SMART CARD AFE DUAL 28SOIC
其它名稱： 90-08005#KIT
Voltage Supervisor
The voltage supervisor monitors the VDD supply. A
220s reset pulse (tW) is used internally to keep the
device inactive during power-on or power-off of the
VDD supply. See Figure 2.
The IC card interface remains inactive regardless of the
levels on the command lines until duration tW after VDD
has reached a level higher than VTH2 + VHYS2. When
VDD falls below VTH2, the device executes a card
deactivation sequence if the card interface is active.
Clock Circuitry
The card clock signal (CLKA/CLKB) is derived from a
clock signal input to XTAL1 or from a crystal operating
at up to 20MHz connected between XTAL1 and XTAL2.
The output clock frequency of CLK_ is selectable
through inputs CLKDIV1 and CLKDIV2. The CLK signal
frequency can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8.
See Table 1 for the frequency generated on the CLK_
signal given the inputs to CLKDIV1 and CLKDIV2.
Note that CLKDIV1 and CLKDIV2 must not be changed
simultaneously; a delay of 10ns minimum between
changes is needed. The minimum duration of any state
of CLK_ is eight periods of XTAL1.
The frequency change is synchronous: during a transi-
tion of the clock divider, no pulse is shorter than 45% of
the smallest period, and the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change
is effective for only eight periods of XTAL1 after the
command.
The fXTAL duty factor depends on the input signal on
XTAL1. To reach a 45% to 55% duty factor on CLK_,
XTAL1 should have a 48% to 52% duty factor with tran-
sition times less than 5% of the period.
With a crystal, the duty factor on CLK_ can be 45% to
55% depending on the circuit layout and on the crystal
characteristics and frequency. In other cases, the duty
factor on CLK_ is guaranteed between 45% and 55% of
the clock period.
I/O Transceivers
I/O_ and I/OIN are pulled high with an 11k
Ω resistor
(I/O_ to VCC_ and I/OIN to VDD) in the inactive state.
The first side of the transceiver to receive a falling edge
becomes the master. When a falling edge is detected
(and the master is decided), the detection of falling
edges on the line of the other side is disabled; that side
then becomes a slave. After a time delay tD(EDGE), an n
transistor on the slave side is turned on, thus transmit-
ting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay tPU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high tran-
sitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
DS8005
Smart Card Interface
10
______________________________________________________________________________________
VDD
ALARM
(INTERNAL SIGNAL)
POWER ON
tW
POWER OFF
VTH2 + VHYS2
VTH2
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
Table 1. Clock Frequency Selection
CLKDIV1
CLKDIV2
fCLK
0
fXTAL/8
0
1
fXTAL/4
1
fXTAL/2
1
0
fXTAL
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