參數(shù)資料
型號(hào): DS75LVU+T&R
廠商: Maxim Integrated
文件頁數(shù): 6/13頁
文件大?。?/td> 275K
描述: IC SENSOR TEMP DIGITAL 8MSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 3,000
功能: 溫度計(jì),恒溫計(jì)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -55°C ~ 125°C
精確度: ±3°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),比較器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報(bào):
輸出風(fēng)扇:
電源電壓: 1.7 V ~ 3.7 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-uMAX
包裝: 帶卷 (TR)
DS75LV: Digital Thermometer and Thermostat
 
6 of 13   
 
 
 
 
OPERATION?/SPAN>THERMOSTAT
The DS75LV thermostat has two operating modes, comparator mode and interrupt mode, which activate and
deactivate the open-drain thermostat output (O.S.) based on user-programmable trip-points (T
OS
 and T
HYST
). The
DS75LV powers up with the thermostat in comparator mode, active-low O.S. polarity, over-temperature trip-point
(T
OS
) register set to 80C, and the hysteresis trip-point (T
HYST
) register set to 75篊. If these power-up settings are
compatible with the application, the DS75LV can be used as a standalone thermostat (i.e., no 2wire
communication required). If interrupt mode operation, active-high O.S. polarity or different T
OS
 and T
HYST
values are
desired, they must be programmed after power-up, so standalone operation is not possible.
In both operating modes, the user can program the thermostat fault tolerance, which sets how many consecutive
temperature readings (1, 2, 4, or 6) must fall outside of the thermostat limits before the thermostat output is
triggered. The fault tolerance is set by the F1 and F0 bits in the configuration register. At power-up the fault
tolerance is set to 1.
The data format of the T
OS
 and T
HYST
 registers is identical to that of the temperature register (see Figure 3), i.e., a
two-byte twos complement representation of the trip-point temperature in degrees centigrade with bits 3 through 0
hardwired to 0. After every temperature conversion, the measurement is compared to the values stored in the T
OS
 
and T
HYST
 registers. The O.S. output is updated based on the result of the comparison and the operating mode of
the IC. The number of T
OS
  and T
HYST
  bits used during the thermostat comparison is equal to the conversion
resolution set by the R1 and R0 bits in the configuration register. For example, if the resolution is 9 bits, only the 9
MSbs of T
OS
 and T
HYST
 will be used by the thermostat comparator.
The active state of the O.S. output can be changed via the POL bit in the configuration register. The power-up
default is active low.
If the user does not wish to use the thermostat capabilities of the DS75LV, the O.S. output should be left floating.
Note that if the thermostat is not used, the T
OS
 and T
HYST
 registers can be used for general storage of system data.
Comparator Mode: When the thermostat is in comparator mode, O.S. can be programmed to operate with any 
amount of hystoresis. The O.S. output becomes active when the measured temperature exceeds the T
OS
 value a
consecutive number of times as defined by the F1 and F0 fault tolerance (FT) bits in the configuration register. O.S.
then stays active until the first time the temperature falls below the value stored in T
HYST
. Putting the device into
shutdown mode does not clear O.S. in comparator mode. Thermostat comparator mode operation with FT = 2 is
illustrated in Figure 4.
Interrupt Mode: In interrupt mode, the O.S. output first becomes active when the measured temperature exceeds 
the T
OS
 value a consecutive number of times equal to the FT value in the configuration register. Once activated,
O.S. can only be cleared by either putting the DS75LV into shutdown mode or by reading from any register
(temperature, configuration, T
OS
, or T
HYST
) on the device. Once O.S. has been deactivated, it will only be
reactivated when the measured temperature falls below the T
HYST
 value a consecutive number of times equal to the
FT value. Again, O.S can only be cleared by putting the device into shutdown mode or reading any register. Thus,
this interrupt/clear process is cyclical between T
OS
and T
HYST
 events (i.e, T
OS
, clear, T
HYST
, clear, T
OS
, clear, T
HYST
,
clear, etc.). Thermostat interrupt mode operation with FT = 2 is illustrated in Figure 4.
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