參數(shù)資料
型號: DS4776D+
廠商: Maxim Integrated Products
文件頁數(shù): 5/8頁
文件大?。?/td> 0K
描述: IC OSC CLOCK 77.76MHZ 10-LCCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 32
類型: 時鐘振蕩器
頻率: 77.76MHz
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 52mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LCCC 裸露焊盤
包裝: 管件
供應(yīng)商設(shè)備封裝: 10-LCCC
安裝類型: 表面貼裝
DS4125–DS4776
DS4-XO Series Crystal Oscillators
_______________________________________________________________________________________
5
Detailed Description
The devices consist of a fundamental-mode, AT-cut
crystal and a synthesizer IC that can synthesize any
one of these frequencies: 77.76MHz, 125MHz,
150MHz, 155.52MHz, 156.25MHz, 160MHz, 250MHz,
300MHz, 311.04MHz, 312.5MHz, and 622.08MHz.
All devices support two types of differential output dri-
vers: LVDS and LVPECL. When the OE signal is low,
LVPECL outputs go to the PECL_BIAS level of
VCC - 2.0V, while the LVDS outputs are a logical one.
See Figures 2 and 3 for an LVDS and LVPECL output
timing diagram.
Additional Information
For more available frequencies, refer to the DS4106
data sheet at www.maxim-ic.com/DS4106.
X1
X2
TRI-
STATE
PHASE
DET
FILTER
LC-VCO
/n
OUTSELN
/m
OUTDRV
VCC
GND
OE
OUTP
OUTN
DS4125–DS4776
Figure 1. Functional Diagram
OE
OUTP
tP1A
tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
OE
OUTP
PECL_BIAS
OUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
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參數(shù)描述
DS4776D+ 功能描述:標(biāo)準(zhǔn)時鐘振蕩器 DS4-XO Series Clock Oscillator RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
DS4776P+ 功能描述:標(biāo)準(zhǔn)時鐘振蕩器 DS4-XO Series Clock Oscillator RoHS:否 制造商:AVX 產(chǎn)品:Standard Clock Oscillators 封裝 / 箱體:7 mm x 5 mm 頻率:75 MHz 頻率穩(wěn)定性:50 PPM 電源電壓:2.5 V 負(fù)載電容: 端接類型:SMD/SMT 最小工作溫度:0 C 最大工作溫度:+ 70 C 輸出格式:LVDS 尺寸: 封裝:Reel 系列:
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