參數資料
型號: DS4100H+
廠商: Maxim Integrated Products
文件頁數: 3/7頁
文件大?。?/td> 0K
描述: IC OSC CLOCK 100MHZ 10-LCCC
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 35
類型: 時鐘振蕩器
頻率: 100MHz
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 71mA
工作溫度: -40°C ~ 85°C
封裝/外殼: 10-LCCC 裸露焊盤
包裝: 管件
供應商設備封裝: 10-LCCC
安裝類型: 表面貼裝
產品目錄頁面: 1434 (CN2011-ZH PDF)
DS4100H
100MHz HCSL Clock Oscillator
_______________________________________________________________________________________
3
Note 1: All voltages are referenced to ground.
Note 2: With 50
Ω load to ground on each output pin.
Note 3: Guaranteed by design and not production tested.
Note 4: tPZL is defined as the time at which VOE = 1.0V on the rising edge of OE to the time at which VOUTP or VOUTN = 0.1VOH on
the falling edge of OUTP or OUTN.
Note 5: tPZH is defined as the time at which the voltage on the rising edge of OE is equal to 1.0V to the time at which VOUTP or
VOUTN = 0.9VOH on the rising edge of VOUTP or VOUTN.
Note 6: tPZ is defined as the time at which VOE = 1.0V on the falling edge of OE to the time at which both VOUTP and VOUTN are
less than 0.1VOH.
Note 7: Frequency stability is calculated as:
ΔfTOTAL = ΔfTEMP + ΔfVCC x 0.165 + ΔfLOAD + ΔfAGING.
Note 8: Measured with 50mVP-P sinusoidal signal on the supply from 10kHz to 1MHz.
Note 9: Including oscillator startup time and PLL acquisition time measured after VCC reaches 3.0V from power-on.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Disable Time
tPZ
Figure 3 (Note 6)
10
ns
CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN
Clock Output
fOUT
100
MHz
Frequency Stability
Total
f / fO
Over temperature range, aging, load, and supply (Note 7)
-39
+39
ppm
Initial Frequency
Tolerance
f_TOL
VCC = 3.3V, TA = +25°C
±15
ppm
Frequency Stability
vs. Temperature
f / fO | TA VCC = 3.3V
-30
+30
ppm
Frequency Stability
vs. VCC
f / fO | V VCC = 3.3V ±5%
-3
+3
ppm/V
Frequency Stability
vs. Load
f / fO
| LOAD
±10% variation in termination resistance
±1
ppm
Aging (10 Years)
fAGING
-7
+7
ppm
Phase Jitter (RMS)
PJRMS
12kHz to 20MHz
0.9
ps
10kHz
3.0
100kHz
27
200kHz
15
Accumulated
Deterministic Jitter Due
to Power-Supply Noise
(Note 8)
DJPN,P-P
1MHz
7.0
ps
Rise and Fall Time
Mismatching
20% to 80%; CL = 2pF; Figure 2;
2 x (tR - tF) / (tR + tF)
±20
%
Duty Cycle
tDC
Measure at OUTP and OUTN, Figure 2
45
55
%
Oscillation Startup Time
(Note 9)
3
ms
100Hz
-90.0
1kHz
-112
10kHz
-115
100kHz
-123
1MHz
-142
Clock Output SSB
Phase Noise
10MHz
-147
dBc/
Hz
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