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參數(shù)資料
| 型號： | DS3902U-530+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL RESISTER EEPROM 8USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 30k，50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 90-3902T+530 |
DS3902
Dual, NV, Variable Resistors
with User EEPROM
8
_____________________________________________________________________
SDA
SCL
tHD:STA
tLOW
tHIGH
tR
tF
tBUF
tHD:DAT
tSU:DAT
REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
START
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN)
Figure 1. I2C Timing Diagram
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See the timing dia-
gram for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See the timing dia-
gram for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTS are commonly used during read operations to
identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See the timing dia-
gram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 1). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 1) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a write
operation) performs an ACK by transmitting a zero during
the 9th bit. A device performs a NACK by transmitting a one
during the 9th bit. Timing (Figure 1) for the ACK and NACK
is identical to all other bit writes. An ACK is the acknowledg-
ment that the device is properly receiving data. A NACK is
used to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8-bits of informa-
tion transferred from the master to the slave (MSB first)
plus a 1-bit acknowledgement from the slave to the
master. The 8-bits transmitted by the master are done
according to the bit write definition and the acknowl-
edgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (MSB first) from the slave to the
master are read by the master using the bit read defini-
tion above, and the master transmits an ACK using the
bit write definition to receive additional data bytes. The
master must NACK the last byte read to terminate com-
munication so the slave will return control of SDA to the
master.
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