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參數(shù)資料
| 型號： | DS3674J |
| 英文描述： | Quad Clock Driver |
| 中文描述： | 四時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 181K |
| 代理商： | DS3674J |
DS1672
7 of 12
Data valid:
The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the high period of the clock signal. The data on the line must be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between the START and the STOP conditions is not limited, and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge:
Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with
this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
DATA TRANSFER ON 2-WIRE SERIAL BUS
Figure 4
MSB
slave address
R/W
direction
bit
SDA
SCL
START
CONDITION
1
2
6
7
8
9
1
2
8
9
STOP CONDITION
OR
REPEATED
START CONDITION
3 - 8
acknowledgement
signal from receiver
acknowledgement
signal from receiver
ACK
ACK
repeated if more bytes
are transferred
Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of
the R/
W
bit, two types of data transfer are possible:
1.
Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte.
2.
Data transfer from a slave transmitter to a master receiver.
The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
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PDF描述 |
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| DS3674N | Audio Amplifier 1.6W, diff., gain adj MSOP 10-pin |
| DS1672U-33 | Low Voltage Serial Timekeeping Chip |
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| DS1672S-2 | Low Voltage Serial Timekeeping Chip |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3674J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS3674N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS3674N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS3674N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Clock Driver |
| DS3675J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Memory Driver |
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