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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� DS3514T+T&R
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 8/21闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC I2C GAMMA/VCOM BUFF 48-TQFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
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鎳�(y墨ng)鐢細 TFT-LCD 闈㈡澘锛氫冀鐟珐娌栧櫒锛孷COM 椹�(q奴)鍕曞櫒
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闆昏矾鏁�(sh霉)锛� 14
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闆绘祦 - 杓稿嚭 / 閫氶亾锛� 4mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 9 V ~ 15 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-WFQFN 瑁搁湶鐒婄洡
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-TQFN-EP锛�7x7锛�
鍖呰锛� 甯跺嵎 (TR)
DS3514
I2C Gamma and VCOM Buffer with EEPROM
16
______________________________________________________________________________________
Control Register 48h: Control Register (CR)
FACTORY DEFAULT
20h
MEMORY TYPE
NV
48h
x
BIAS1
BIAS0
x
MODE1
MODE0
BIT 7
BIT 0
Bits 7:6
Reserved
Bits 5:4
VCOM and Gamma Bias Current Control Bits (BIAS[1:0]):
00 = 60%
01 = 80%
10 = 100% (default)
11 = 150%
Bits 3:2
Reserved
Bits 1:0
DS3514 Mode (MODE[1:0]):
00 = S0/S1 pins are used to select the desired bank (A鈥揇) (default).
01 = SOFT S0/S1 (bits) are used to select the desired bank (A鈥揇).
1X = Latch A is used to control the DACs.
Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins
FACTORY DEFAULT
鈥�
MEMORY TYPE
Read Only
4Ah
LD
x
S1
S0
BIT 7
BIT 0
This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are
arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h鈥�59h). This
arrangement is applicable for all the EEPROM data for all gamma channels.
GDATx Register: EEPROM Data for the Gamma Channels
FACTORY DEFAULT
8000h
MEMORY TYPE
NV
58h
GDAT[9]
GDAT[8]
GDAT[7]
GDAT[6]
GDAT[5]
GDAT[4]
GDAT[3]
GDAT[2]
59h
GDAT[1]
GDAT[0]
x
BIT 7
BIT 0
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DS3516FP000 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:30A,CON,4P5W,MG,516,3PY120V
DS3516FR000 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:30A,REC,4P5W,MG,516,3PY120V
DS3516FRAB0 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:30A,REC,4P5W,MG,516,AB0,3PY120V
DS3516FRS00 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:30A,REC,4P5W,MG,516,STR,3PY120V
DS3516FRSB0 鍒堕€犲晢:Thomas & Betts 鍔熻兘鎻忚堪:30A,REC,4P5W,MG,516,SB0,3PY120V