參數(shù)資料
型號(hào): DS3253DK
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 32/71頁(yè)
文件大?。?/td> 0K
描述: KIT DEMO FOR DS3253
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS3253
DS3251/DS3252/DS3253/DS3254
38 of 71
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling
CS high. In response to early terminations, the DS325x resets its SPI interface logic and waits for the start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the current data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS325x is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS325x is transmitting.
AC Timing. See Table 17-I and Figure 17-5 for AC timing specifications for the SPI interface.
Figure 15-1. SPI Clock Polarity and Phase Options
MSB
LSB
65
4
3
21
CS
SCK
SDI/SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
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