參數(shù)資料
型號(hào): DS32506N#
廠商: Maxim Integrated Products
文件頁數(shù): 95/130頁
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 60
類型: 線路接口裝置(LIU)
規(guī)程: IEEE 1149.1
電源電壓: 1.8V, 3.3V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
67 of 130
Register Name:
PORT.ISR
Register Description:
Port Interrupt Status Register
Register Address:
n * 80h + 10h
Bit #
15
14
13
12
11
10
9
8
Name
Bit #
7
6
5
4
3
2
1
0
Name
LDSR
LIUSR
BSR
PSR
Bit 3: Line Decoder Status Register Interrupt Status (LDSR).
This bit is set when any of the latched status
register bits in the B3ZS/HDB3 Line Decoder block are set and enabled for interrupt. When set, this bit causes an
interrupt if PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are both set. See Section 8.10.
Bit 2: LIU Status Register Interrupt Status (LIUSR).
This bit is set when any of the latched status register bits in
the LIU block are set and enabled for interrupt. When set, this bit causes an interrupt if PORT.ISRIE:LIUSRIE and
GLOBAL.ISRIE: PnISRIE are both set. See Section 8.10.
Bit 1: BERT Status Register Interrupt Status (BSR).
This bit is set when any of the latched status register bits in
the BERT block are set and enabled for interrupt. When set, this bit causes an interrupt if PORT.ISRIE:BSRIE and
GLOBAL.ISRIE: PnISRIE are both set. See Section 8.10.
Bit 0: Port Status Register Interrupt Status (PSR).
This bit is set when any of the latched status register bits in
the port latched status register (PORT.SRL) are set and enabled for interrupt. When set, this bit causes an interrupt
if PORT.ISRIE:PSRIE and GLOBAL.ISRIE: PnISRIE are both set. See Section 8.10.
Register Name:
PORT.ISRIE
Register Description:
Port Interrupt Status Register Interrupt Enable
Register Address:
n * 80h + 14h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
LDSRIE
LIUSRIE
BSRIE
PSRIE
Default
0
Bit 3: Line Decoder Status Register Interrupt Enable (LDSRIE).
This bit is the interrupt enable for the
PORT.ISR:LDSR status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 2: LIU Status Register Interrupt Enable (LIUSRIE).
This bit is the interrupt enable for the PORT.ISR:LIUSR
status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 1: BERT Status Register Interrupt Enable (BSRIE).
This bit is the interrupt enable for the PORT.ISR:BSR
status bit.
0 = mask the interrupt
1 = enable the interrupt
Bit 0: Port Status Register Interrupt Enable (PSRIE).
This bit is the interrupt enable for the PORT.ISR:PSR
status bit.
0 = mask the interrupt
1 = enable the interrupt
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