參數(shù)資料
型號(hào): DS3234SN#T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/21頁(yè)
文件大?。?/td> 0K
描述: IC RTC SPI BUS W/TCXO 20-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,NVSRAM,方波輸出,TCXO/晶體
存儲(chǔ)容量: 256B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: SPI
電源電壓: 2 V ~ 5.5 V
電壓 - 電源,電池: 2 V ~ 3.8 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 帶卷 (TR)
DS3234
Extremely Accurate SPI Bus RTC with
Integrated Crystal and SRAM
18
____________________________________________________________________
Address and data bytes are shifted MSB first into the
serial data input (DIN) and out of the serial data output
(DOUT). Any transfer requires the address of the byte
to specify a write or read, followed by one or more
bytes of data. Data is transferred out of the DOUT pin
for a read operation and into the DIN for a write opera-
tion (Figures 3 and 4).
The address byte is always the first byte entered after
CS is driven low. The most significant bit of this byte
determines if a read or write takes place. If the MSB is
0, one or more read cycles occur. If the MSB is 1, one
or more write cycles occur.
MODE
CS
SCLK
DIN
DOUT
Disable
H
Input Disabled
High Impedance
*CPOL = 1, SCLK Rising
Write
L
CPOL = 0, SCLK Falling
Data Bit Latch
High Impedance
CPOL = 1, SCLK Falling
Read
L
CPOL = 0, SCLK Rising
X
Next Data Bit Shift**
Read Invalid Location
L
Don’t Care
High Impedance
Table 3. SPI Pin Function
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SCLK
DIN
DOUT
HIGH IMPEDANCE
Figure 3. SPI Single-Byte Write
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SCLK
DIN
DOUT
HIGH IMPEDANCE
R/W
Figure 4. SPI Single-Byte Read
*
CPOL is the clock-polarity bit set in the control register of the host microprocessor.
**
DOUT remains at high impedance until 8 bits of data are ready to be shifted out during a read.
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