I2C communications could beco" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS3232SN#T&R
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/19闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC RTC W/TCXO 20-SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
椤炲瀷锛� 鏅�(sh铆)閻�/鏃ユ
鐗归粸(di菐n)锛� 璀﹀牨(b脿o)鍣�锛岄枏骞达紝鏂规尝杓稿嚭锛孴CXO/鏅堕珨
瀛樺劜(ch菙)瀹归噺锛� 236B
鏅�(sh铆)闁撴牸寮忥細 HH:MM:SS锛�12/24 灏忔檪(sh铆)锛�
鏁�(sh霉)鎿�(j霉)鏍煎紡锛� YY-MM-DD-dd
鎺ュ彛锛� I²C锛�2 绶氫覆鍙�
闆绘簮闆诲锛� 2.3 V ~ 5.5 V
闆诲 - 闆绘簮锛岄浕姹狅細 2.3 V ~ 5.5 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-SOIC W
鍖呰锛� 甯跺嵎 (TR)
event, it is possible that the microcontroller and DS3232
I2C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the DS3232. When the microcontroller resets, the
DS3232 I2C interface may be placed into a known state
by toggling SCL until SDA is observed to be at a high
level. At that point the microcontroller should pull SDA
low while SCL is high, generating a START condition.
If SCL is held low for greater than tIF, the internal I2C
interface is reset. This limits the minimum frequency at
which the I2C interface can be operated. If data is
being written to the device when the interface timeout is
exceeded, prior to the acknowledge, the incomplete
byte of data is not written.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3232 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Figure 1. Address Map for DS3232 Timekeeping Registers and SRAM
Note: Unless otherwise specified, the registers鈥� state is not defined when power is first applied.
ADDRESS
BIT 7
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
FUNCTION
RANGE
00h
0
10 Seconds
Seconds
00鈥�59
01h
0
10 Minutes
Minutes
00鈥�59
AM/PM
02h
0
12/24
20 Hour
10 Hour
Hour
Hours
1鈥�12 + AM/PM
00鈥�23
03h
0
Day
1鈥�7
04h
0
10 Date
Date
1鈥�31
05h
Century
0
10 Month
Month
Month/
Century
01鈥�12 +
Century
06h
10 Year
Year
00鈥�99
07h
A1M1
10 Seconds
Seconds
Alarm 1 Seconds
00鈥�59
08h
A1M2
10 Minutes
Minutes
Alarm 1 Minutes
00鈥�59
AM/PM
09h
A1M3
12/24
20 Hour
10 Hour
Hour
Alarm 1 Hours
1鈥�12 + AM/PM
00鈥�23
Day
Alarm 1 Day
1鈥�7
0Ah
A1M4
DY/DT
10 Date
Date
Alarm 1 Date
1鈥�31
0Bh
A2M2
10 Minutes
Minutes
Alarm 2 Minutes
00鈥�59
AM/PM
0Ch
A2M3
12/24
20 Hour
10 Hour
Hour
Alarm 2 Hours
1鈥�12 + AM/PM
00鈥�23
Day
Alarm 2 Day
1鈥�7
0Dh
A2M4
DY/DT
10 Date
Date
Alarm 2 Date
1鈥�31
0Eh
EOSC
BBSQW
CONV
RS2
RS1
INTCN
A2IE
A1IE
Control
鈥�
0Fh
OSF
BB32kHzCRATE1
CRATE0
EN32kHz
BSY
A2F
A1F
Control/Status
鈥�
10h
SIGN
DATA
Aging Offset
鈥�
11h
SIGN
DATA
MSB of Temp
鈥�
12h
DATA
0
LSB of Temp
鈥�
13h
0
Not used
Reserved for
test
14h鈥�0FFh
x
SRAM
00h鈥�0FFh
DS3232
Maxim Integrated
11
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
DS3234S# IC RTC W/TCXO 20-SOIC
DS32C35-33#T&R IC RTC ACCURATE I2C 3.3V 20-SOIC
DS3911T+ IC DAC 10BIT I2C QUAD 14TDFN
DS4000KI/WBGA IC OSC TCXO 19.44MHZ 24-BGA
DS4026S+WCN IC OSC TCXO 25MHZ 16-SOIC
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
DS3234 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM
DS3234_07 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM
DS3234_08 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM
DS3234_10 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM
DS3234_BREAKOUT_ 鍒堕€犲晢:MCM 鍔熻兘鎻忚堪:DS3234 BREAKOUT BOARD 鍒堕€犲晢:PREMIER FARNELL 鍔熻兘鎻忚堪:DS3234 BREAKOUT BOARD