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參數(shù)資料
| 型號： | DS3232S#T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC W/TCXO 20-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出，TCXO/晶體 |
| 存儲容量： | 236B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
...
A
XXXXXXXX
A
1101000
S
0
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
P
<R/W>
<WORD ADDRESS (n)>
<DATA (n)>
<DATA (n + 1)>
<DATA (n + X)
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
MASTER TO SLAVE
SLAVE TO MASTER
<SLAVE
ADDRESS>
Figure 3. Data Write—Slave Receiver Mode
...
A
XXXXXXXX
A
1101000
S
1
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
P
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
MASTER TO SLAVE
SLAVE TO MASTER
<R/W>
<DATA (n)>
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
<SLAVE
ADDRESS>
Figure 4. Data Read—Slave Transmitter Mode
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
<R/W>
<WORD ADDRESS (n)>
<SLAVE ADDRESS (n)>
<SLAVE
ADDRESS>
<R/W>
A
XXXXXXXX
A
1101000
SSr
0
A
1
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
MASTER TO SLAVE
SLAVE TO MASTER
A
XXXXXXXX
A
XXXXXXXX
A
XXXXXXXX
A
P
<DATA (n)>
<DATA (n + 1)>
<DATA (n + 2)>
<DATA (n + X)>
...
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
DS3232
Maxim Integrated
17
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