
DS3181/DS3182/DS3183/DS3184
239
Register Name:
PORT.ISR
Register Description:
Port Interrupt Status Register
Register Address:
(0,2,4,6)50h
Bit #
15
14
13
12
11
10
9
8
Name
—
PSR
LCSR
Bit #
7
6
5
4
3
2
1
0
Name
TTSR
FSR
HSR
BSR
SFSR
CPSR
PPSR
FMSR
Bit 9: Port Status Register Interrupt Status (PSR) This bit is set when any of the latched status register bits, that
are enabled for interrupt, in the PORT.SRL register are set. The interrupt pin will be driven when this bit is set and
Bit 8: Line Code Status Register Interrupt Status (LCSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the B3ZS/HDB3 Line Encoder/Decoder block are set. The interrupt pin will be
driven when this bit is set and the corresponding
GL.ISRIE.PISRIE[4:1] is set.
Bit 7: Trail Trace Status Register Interrupt Status (TTSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the trail trace block are set. The interrupt pin will be driven when this bit is set
Bit 6: FEAC Status Register Interrupt Status (FSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the FEAC block are set. The interrupt pin will be driven when this bit is set and the
Bit 5: HDLC Status Register Interrupt Status (HSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the HDLC block are set. The interrupt pin will be driven when this bit is set and the
Bit 4: BERT Status Register Interrupt Status (BSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the BERT block are set. The interrupt pin will be driven when this bit is set and the
Bit 3: System FIFO Status Register Interrupt Status (SFSR) This bit is set when any of the latched status
register bits, that are enabled for interrupt, in either the transmit or receive FIFO block are set. The interrupt pin will
be driven when this bit is set and the corresponding
GL.ISRIE.PISRIE[4:1] is set.
Bit 2: Cell/Packet Status Register Interrupt Status (CPSR) This bit is set when any of the latched status register
bits, that are enabled for interrupt, in the active transmit or receive cell processor or packet processor block are set.
The interrupt pin will be driven when this bit is set and the corresponding
GL.ISRIE.PISRIE[4:1] is set.
Bit 1: PLCP Status Register Interrupt Status (PPSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active PLCP block are set. The interrupt pin will be driven when this bit is set
Bit 0: Framer Status Register Interrupt Status (FMSR) This bit is set when any of the latched status register bits,
that are enabled for interrupt, in the active DS3 or E3 framer block are set. The interrupt pin will be driven when this