
DS3171/DS3172/DS3173/DS3174
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10.8 Trail Trace Controller
10.8.1 General Description
Each port has a dedicated Trail Trace Buffer for E3-G.832 link management
The Trail Trace Controller performs extraction and storage of the incoming G.832 trail access point identifier in a
16-byte receive register.
The Trail Trace Controller extracts/inserts E3-G.832 trail access point identifiers using a 16-byte register(one for
transmit, one for receive).
The Trail Trace Controller demaps a 16-byte trail trace identifier from the E3-G.832 TR Byte of the overhead in the
receive direction and maps a trace identifier into the E3-G.832 datastream in the transmit direction.
The receive direction inputs the trace ID data stream, performs trace ID processing, and stores the trace identifier
data in the data storage using line timing. It removes trace identifier data from the data storage and outputs the
trace identifier data to the microprocessor via the microprocessor interface using register timing. The data is forced
to all ones during LOS, LOF and AIS detection to eliminate false messages
The transmit direction inputs the trace identifier data from the microprocessor via the microprocessor interface and
stores the trace identifier data in the data storage using register timing. It removes the trace identifier data from the
data storage, performs trace ID processing, and outputs the trace ID data stream. Refer to
Figure 10-21
for the
location of the Trail Trace Controller with the DS317x devices.
Figure 10-21. Trail Trace Controller Block Diagram
10.8.2 Features
Programmable trail trace ID
– The trail trace ID controller can be programmed to handle a 16-byte trail trace
identifier (trail trace mode).
Programmable transmit trace ID
– All sixteen bytes of the transmit trail trace identifier are programmable.
Programmable receive expected trace ID
– A 16-byte expected trail trace identifier can be programmed.
Both a mismatch and unstable indication are provided.
Programmable trace ID multi-frame alignment
– The transmit side can be programmed to perform trail trace
multi-frame alignment insertion. The receive side can be programmed to perform trail trace multi-frame
synchronization.
Programmable bit reordering
– The trace identifier data can be output MSB first or LSB first from the data
storage.
Programmable data inversion
– The trace identifier data can be inverted immediately after trace ID
processing on the transmit side, and immediately before trail ID processing on the receive side.
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
Microprocessor
Interface
HDLC
FEAC
L
D
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
DS3/E3
Receive
LIU
TUA1
Clock Rate
Adapter
TX BERT
RX BERT
P
A
UA1
GEN
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder