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DS3150
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SIGNAL DESCRIPTIONS Table 2A (cont.)
Signal
Name
I/O
Description
PRBS
O3
PRBS Detector. This signal reports the status of the PRBS Detector. The PRBS
detector will constantly search for either a 215 – 1 (T3 or STS-1) or 223 – 1 (E3)
psuedo random bit sequence. This signal will remain high when the PRBS detector is
out of synchronization. When the PRBS detector syncs to the PRBS, this signal will
go low and will create a high pulse (synchronous with RCLK) for each bit error
detected. See Figures 1F and 1G for more details. If EFE = 0, then this signal is tri-
stated. This signal is not bonded out in the PLCC package.
RCLK
O
Receive Clock. The recovered clock is output at this pin. When the DS3150
experiences a Loss Of Signal (LOS* = 0), the clock applied at MCLK (or TCLK if
MCLK is high/floating or the internal oscillator if MCLK is tied low) appears at this
signal. The recovered data is updated at the RPOS/RNRZ and RNEG/RLCV outputs
on either the falling edge of RCLK (ICE = 0 or 1) or the rising edge of RCLK (ICE =
FLOAT).
RMON
I3
Receive Monitor Mode. This input determines whether or not a 20 dB flat gain will
be applied to the incoming signal before it is fed to the receive equalizer. This mode
is invoked when the device is being used to monitor signals that have been resistively
attenuated by a monitor jack. In this mode, the maximum input signal allowed at
RX+ and RX– is reduced by 20 dB. This input also controls the jitter attenuator. See
Table 2C.
0 = disable the 20 dB gain, disable RX jitter attenuation
1 = enable the 20 dB gain, disable RX jitter attenuation
Float = disable the 20 dB gain, enable RX jitter attenuation
RNEG/
RLCV
O
Receive Negative Data or Receive Line Code Violation. When the B3ZS/HBD3
encoder/decoder is disabled (ZCSE* = 1), RNEG indicates reception of a negative
AMI pulse. When the B3ZS/HDB3 encoder/decoder is enabled (ZCSE* = 0), the
NRZ data stream will be output on RNRZ while RLCV is pulsed high whenever the
decoder sees a bipolar violation that is not part of a valid B3ZS/HDB3 codeword or a
zero that results in an excessive zero occurrence. This signal will be updated either on
the rising edge of RCLK (ICE = Float) or the falling edge of RCLK (ICE = 0 or 1).
RPOS/
RNRZ
O
Receive Positive or Receive NRZ Data. When the B3ZS/HBD3 encoder/decoder is
disabled (ZCSE* = 1), this signal indicates reception of a positive AMI pulse. When
the B3ZS/HDB3 encoder/decoder is enabled (ZCSE* = 0), this signal will contain the
recovered NRZ data stream. This signal will be updated either on the rising edge of
RCLK (ICE = Float) or the falling edge of RCLK (ICE = 0 or 1).
RX+
RX–
I
Receive Analog Inputs. These differential AMI inputs are coupled to the T3, STS-1,
or E3 75
coax line via a 1:2 step-up transformer. See Figure 1B for details.
TCLK
I
Transmit Clock. A T3 (44.736 MHz
± 20 ppm), E3 (34.368 MHz ± 20 ppm) or
STS-1 (51.840
± 20 ppm) clock should be applied at this signal. Data to be
transmitted will be clocked into the device at TPOS/TNRZ and TNEG either on a
rising edge of TCLK (ICE = 0) or falling edge of TCLK (ICE = 1 or FLOAT). The
duty cycle on TCLK is not restricted as long it meets the high and low times listed in
Section 3.
TDS0
I
Transmit Data Select Bit 0. If EFE = 1, this signal and signals TDS1 and TESS
select the source of the transmit data (see Table 2B). If EFE = 0, this signal is
ignored.