參數(shù)資料
型號(hào)： DS28EA00U+T&R
廠(chǎng)商： Maxim Integrated
文件頁(yè)數(shù)： 24/29頁(yè)
文件大小： 328K
描述： IC THERMOMETER 1-WIRE 8-USOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 3,000
功能： 溫度計(jì)，恒溫計(jì)
傳感器類(lèi)型： 內(nèi)部
感應(yīng)溫度： -40°C ~ 85°C
精確度： ±0.5°C（最小值）
拓?fù)洌?/td> 寄存器庫(kù)，變簽式暫存器
輸出類(lèi)型： 數(shù)字
輸出警報(bào)： 是
輸出風(fēng)扇： 無(wú)
電源電壓： 3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-uMAX
包裝： 帶卷 (TR)
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
24
Maxim Integrated
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the V
TH
threshold before the write-
one low time t
W1LMAX
is expired. For a write-zero time
slot, the voltage on the data line must stay below the
V
TH
threshold until the write-zero low time t
W0LMIN
is
expired. For the most reliable communication, the volt-
age on the data line should not exceed V
ILMAX
during
the entire t
W0L
or t
W1L
window. After the V
TH
threshold
has been crossed, the DS28EA00 needs a recovery
time t
REC
before it is ready for the next time slot.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below V
TL
until the read low time t
RL
is expired. During the t
RL
window, when responding with a 0, the DS28EA00
starts pulling the data line low; its internal timing gener-
ator determines when this pulldown ends and the volt-
age starts rising again. When responding with a 1, the
DS28EA00 does not hold the data line low at all, and
the voltage starts rising as soon as t
RL
is over.
The sum of t
RL
+ ?(rise time) on one side and the inter-
nal timing generator of the DS28EA00 on the other side
define the master sampling window (t
MSRMIN
to
t
MSRMAX
) in which the master must perform a read from
the data line. For the most reliable communication, t
RL
should be as short as permissible, and the master
should read close to but no later than t
MSRMAX
. After
reading from the data line, the master must wait until
t
SLOT
is expired. This guarantees sufficient recovery time
t
REC
for the DS28EA00 to get ready for the next time slot.
Note that t
REC
specified herein applies only to a single
DS28EA00 attached to a 1-Wire line. For multidevice
configurations, t
REC
needs to be extended to accommo-
date the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup dur-
ing the 1-Wire recovery time such as the DS2482-x00 or
DS2480B 1-Wire line drivers can be used.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible
only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are suscep-
tible to noise of various origins. Depending on the phys-
ical size and topology of the network, reflections from
end points and branch points can add up, or cancel
each other to some extent. Such reflections are visible
as glitches or ringing on the 1-Wire communication line.
Noise coupled onto the 1-Wire line from external
sources can also result in signal glitching. A glitch dur-
ing the rising edge of a time slot can cause a slave
device to lose synchronization with the master and,
consequently, result in a Search ROM command com-
ing to a dead end or cause a device-specific function
command to abort. For better performance in network
applications, the DS28EA00 uses a new 1-Wire front-
end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front-end of the DS28EA00 differs from tra-
ditional slave devices in four characteristics:
1)  The falling edge of the presence pulse has a con-
trolled slew rate. This provides a better match to the
line impedance than a digitally switched transistor,
converting the high-frequency ringing known from
traditional devices into a smoother low-bandwidth
transition. The slew-rate control is specified by the
parameter t
FPD
, which has different values for stan-
dard and overdrive speed.
2)  There is additional lowpass filtering in the circuit
that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-fre-
quency noise. This additional filtering does not
apply at overdrive speed.
3)  There is a hysteresis at the low-to-high switching
threshold V
TH
. If a negative glitch crosses V
TH
but
does not go below V
TH
- V
HY
, it is not recognized
(Figure 14, Case A). The hysteresis is effective at
any 1-Wire speed.
4)  There is a time window specified by the rising edge
hold-off time t
REH
during which glitches are
ignored, even if they extend below V
TH
- V
HY
threshold (Figure 14, Case B, t
GL
< t
REH
). Deep
voltage droops or glitches that appear late after
crossing the V
TH
threshold and extend beyond the
t
REH
window cannot be filtered out and are taken as
the beginning of a new time slot (Figure 14, Case C,
t
GL
e t
REH
).
Devices that have the parameters V
HY
and t
REH
speci-
fied in their electrical characteristics use the improved
1-Wire front-end.
Sequence Discovery Procedure
Precondition: The PIOB pin (EN) of the first device in
the chain is at logic 0. The PIOA pin (DONE) of the first
device connects to the PIOB of the second device in
the chain, etc., as shown in Figure 15. The 1-Wire mas-
ter detects the physical sequence of the devices in the
chain by performing the following procedure.
Starting Condition: The master issues a Skip ROM
command followed by a Chain ON command, which
puts all devices in the chain ON state. The pullup
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