
DS26522 Dual T1/E1/J1 Transceiver
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NAME
PIN
TYPE
FUNCTION
TSYSCLK1
H8
TSYSCLK2
H11
I
Transmit System Clock.
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz clock. Only used when the transmit-side elastic store function is
enabled. Should be tied low in applications that do not use the transmit-side elastic
store. This is a common clock that is used for both transmitters. The clock can be
4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
TSYNC1
J7
TSYNC2
F11
I/O
Transmit Synchronization.
A pulse at these pins establishes either frame or
multiframe boundaries for the transmit side. These signals can also be
programmed to output either a frame or multiframe pulse. If these pins are set to
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signaling frames in T1 mode. The operation of these signals is
synchronous with TCLK.
TSSYNCIO1
G7
TSSYNCIO2
F12
I/O
Transmit System Synchronization In.
Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for both transmitters. Should be tied low in
applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out.
If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26522
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG1
H7
TSIG2
E11
I
Transmit Signaling.
When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams
can run up to 16.384MHz.
TCHBLK/
CLK1
F7
TCHBLK/
CLK2
G12
O
Transmit Channel Block/Transmit Channel Block Clock.
A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for per-
channel conditioning.
TCHCLK.
TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of each channel. It can also be programmed to output a gated transmit bit
clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side
elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side
elastic store is enabled. Useful for parallel-to-serial conversion of channel data.