
DS26519 16-Port T1/E1/J1 Transceiver 
3 of 310 
9.9.7
9.9.8
9.9.9
9.9.10
9.9.11
9.9.12
9.9.13
9.9.14
9.9.15
9.9.16
9.9.17
9.10
9.10.1
9.10.2
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
9.13
9.13.1
9.13.2
10.
DEVICE REGISTERS.....................................................................................................108
10.1
R
EGISTER 
L
ISTINGS
.................................................................................................................108
10.1.1
Global Register List............................................................................................................................ 109
10.1.2
Framer Register List........................................................................................................................... 110
10.1.3
LIU and BERT Register List............................................................................................................... 117
10.2
R
EGISTER 
B
IT 
M
APS
 ................................................................................................................118
10.2.1
Global Register Bit Map..................................................................................................................... 118
10.2.2
Framer Register Bit Map.................................................................................................................... 119
10.2.3
LIU Register Bit Map.......................................................................................................................... 128
10.2.4
BERT Register Bit Map...................................................................................................................... 129
10.3
G
LOBAL 
R
EGISTER 
D
EFINITIONS
...............................................................................................130
10.4
F
RAMER 
R
EGISTER 
D
ESCRIPTIONS
...........................................................................................156
10.4.1
Receive Register Descriptions........................................................................................................... 156
10.4.2
Transmit Register Descriptions.......................................................................................................... 214
10.5
LIU R
EGISTER 
D
EFINITIONS
 .....................................................................................................250
10.6
BERT R
EGISTER 
D
EFINITIONS
 .................................................................................................260
11.
FUNCTIONAL TIMING ...................................................................................................268
11.1
T1 R
ECEIVER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
..........................................................................268
11.2
T1 T
RANSMITTER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
 ....................................................................273
11.3
E1 R
ECEIVER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
..........................................................................278
11.4
E1 T
RANSMITTER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
....................................................................282
12.
OPERATING PARAMETERS.........................................................................................287
12.1
T
HERMAL 
C
HARACTERISTICS
....................................................................................................288
12.2
L
INE 
I
NTERFACE 
C
HARACTERISTICS
..........................................................................................288
13.
AC TIMING CHARACTERISTICS..................................................................................289
13.1
M
ICROPROCESSOR 
B
US 
AC C
HARACTERISTICS
........................................................................289
13.1.1
SPI Bus Mode.................................................................................................................................... 289
13.2
JTAG I
NTERFACE 
T
IMING
.........................................................................................................300
Maintenance and Alarms ..................................................................................................................... 72
Alarms.................................................................................................................................................. 75
Error Count Registers .......................................................................................................................... 77
DS0 Monitoring Function...................................................................................................................... 79
Transmit Per-Channel Idle Code Generation ...................................................................................... 80
Receive Per-Channel Idle Code Insertion............................................................................................ 80
Per-Channel Loopback ........................................................................................................................ 80
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 80
T1 Programmable In-Band Loop Code Generator............................................................................... 81
T1 Programmable In-Band Loop Code Detection................................................................................ 82
Framer Payload Loopbacks................................................................................................................. 83
HDLC C
ONTROLLERS
................................................................................................................84
Receive HDLC Controller..................................................................................................................... 84
Transmit HDLC Controller.................................................................................................................... 87
P
OWER
-S
UPPLY 
D
ECOUPLING
....................................................................................................89
L
INE 
I
NTERFACE 
U
NITS 
(LIU
S
)....................................................................................................90
LIU Operation....................................................................................................................................... 92
Transmitter........................................................................................................................................... 93
Receiver............................................................................................................................................... 97
Hitless Protection Switching (HPS).................................................................................................... 101
Jitter Attenuator.................................................................................................................................. 102
LIU Loopbacks................................................................................................................................... 103
B
IT 
E
RROR
-R
ATE 
T
EST 
F
UNCTION 
(BERT)...............................................................................106
BERT Repetitive Pattern Set ............................................................................................................. 107
BERT Error Counter........................................................................................................................... 107