
DS26518 8-Port T1/E1/J1 Transceiver 
3 of 286 
9.9.8
9.9.9
9.9.10
9.9.11
9.9.12
9.9.13
9.9.14
9.9.15
9.9.16
9.9.17
9.10
9.10.1
9.10.2
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
9.13
9.13.1
9.13.2
10.
DEVICE REGISTERS.......................................................................................................97
10.1
R
EGISTER 
L
ISTINGS
...................................................................................................................97
10.1.1
Global Register List.............................................................................................................................. 98
10.1.2
Framer Register List............................................................................................................................. 99
10.1.3
LIU and BERT Register List............................................................................................................... 106
10.2
R
EGISTER 
B
IT 
M
APS
 ................................................................................................................107
10.2.1
Global Register Bit Map..................................................................................................................... 107
10.2.2
Framer Register Bit Map.................................................................................................................... 108
10.2.3
LIU Register Bit Map.......................................................................................................................... 117
10.2.4
BERT Register Bit Map...................................................................................................................... 118
10.3
G
LOBAL 
R
EGISTER 
D
EFINITIONS
...............................................................................................119
10.4
F
RAMER 
R
EGISTER 
D
ESCRIPTIONS
...........................................................................................133
10.4.1
Receive Register Descriptions........................................................................................................... 133
10.4.2
Transmit Register Descriptions.......................................................................................................... 191
10.5
LIU R
EGISTER 
D
EFINITIONS
 .....................................................................................................227
10.6
BERT R
EGISTER 
D
EFINITIONS
 .................................................................................................237
11.
FUNCTIONAL TIMING ...................................................................................................245
11.1
T1 R
ECEIVER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
..........................................................................245
11.2
T1 T
RANSMITTER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
 ....................................................................250
11.3
E1 R
ECEIVER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
..........................................................................255
11.4
E1 T
RANSMITTER 
F
UNCTIONAL 
T
IMING 
D
IAGRAMS
....................................................................259
12.
OPERATING PARAMETERS.........................................................................................264
12.1
T
HERMAL 
C
HARACTERISTICS
....................................................................................................265
12.2
L
INE 
I
NTERFACE 
C
HARACTERISTICS
..........................................................................................265
13.
AC TIMING CHARACTERISTICS..................................................................................266
13.1
M
ICROPROCESSOR 
B
US 
AC C
HARACTERISTICS
........................................................................266
13.1.1
SPI Bus Mode.................................................................................................................................... 266
13.2
JTAG I
NTERFACE 
T
IMING
.........................................................................................................277
14.
Alarms.................................................................................................................................................. 65
Error Count Registers .......................................................................................................................... 67
DS0 Monitoring Function...................................................................................................................... 69
Transmit Per-Channel Idle Code Generation ...................................................................................... 70
Receive Per-Channel Idle Code Insertion............................................................................................ 70
Per-Channel Loopback ........................................................................................................................ 70
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 70
T1 Programmable In-Band Loop Code Generator............................................................................... 71
T1 Programmable In-Band Loop Code Detection................................................................................ 72
Framer Payload Loopbacks................................................................................................................. 73
HDLC C
ONTROLLERS
................................................................................................................74
Receive HDLC Controller..................................................................................................................... 74
Transmit HDLC Controller.................................................................................................................... 77
P
OWER
-S
UPPLY 
D
ECOUPLING
....................................................................................................79
L
INE 
I
NTERFACE 
U
NITS 
(LIU
S
)....................................................................................................80
LIU Operation....................................................................................................................................... 82
Transmitter........................................................................................................................................... 83
Receiver............................................................................................................................................... 86
Hitless Protection Switching (HPS)...................................................................................................... 90
Jitter Attenuator.................................................................................................................................... 91
LIU Loopbacks..................................................................................................................................... 92
B
IT 
E
RROR
-R
ATE 
T
EST 
F
UNCTION 
(BERT).................................................................................95
BERT Repetitive Pattern Set ............................................................................................................... 96
BERT Error Counter............................................................................................................................. 96