參數(shù)資料
型號: DS26504LNB2+
廠商: Maxim Integrated Products
文件頁數(shù): 3/129頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
功能: BITS 元件
接口: 64KCC,E1,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 150mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 管件
包括: *
其它名稱: 90-26504+NB2
DS26504 T1/E1/J1/64KCC BITS Element
100 of 129
15. 64KHZ SYNCHRONIZATION INTERFACE
The 64kHz synchronization interface conforms to Appendix II of G.703. It consists of a composite clock,
where a 64kHz clock signal is generated or decoded, along with embedded frequencies of 8kHz and
400Hz. Those signals consist of AMI code with an 8kHz bipolar violation removed at every 400Hz.
There are two separate modes referred to in the specification, one with both the 64kHz clock and the
8kHz clock, and the second with the 64kHz clock, the 8kHz clock, and the 400Hz clock.
Figure 15-1. 64kHz Composite Clock Mode Signal Format
Violation
No
Violation
No
Violation
125 us
8 kHz
400 Hz
15.1 Receive 64kHz Synchronization Interface Operation
In the receive path, the three clock frequencies are decoded from the AMI waveform with bipolar
violations that is received at the LIU interface. The 8kHz frequency and the 400Hz frequency are decoded
from the presence or absence of bipolar violations as described in G.703.
Table 15-1. Specification of 64kHz Clock Signal at Input Port
Frequency
a) 64kHz + 8kHz, or
b) 64kHz + 8kHz + 400Hz
Signal format
a) AMI with 8kHz bipolar violation,
b) AMI with 8kHz bipolar violation removed at every 400Hz
Alarm condition
Alarm should not be occurred against the amplitude ranged
0.63-1.1 V0-P
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