參數(shù)資料
型號(hào): DS26303L-75+A3
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/101頁(yè)
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 144-LQFP 裸露焊盤
包裝: 托盤
其它名稱: 90-26303+7A3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
14 of 101
NAME
PIN
TYPE
FUNCTION
CLKA
93
O,
tri-state
Clock A.
This output becomes a programmable clock output when
enabled (MC.CLKAE is set). For frequency options, see the CCR
register. This option is not available in hardware mode. If this
option is not used, the pin should be left unconnected.
N.C.
94
I
(pulled
to VSS)
No Connection.
Pin should be left unconnected or grounded.
HARDWARE AND PORT OPERATION
MODESEL
11
I
(pulled
to
VDDIO/2)
Mode Selection.
This pin is used to select the control mode of the
DS26303.
Low → Hardware Mode
VDDIO/2 → Serial Host Mode
High → Parallel Host Mode
Note: When left unconnected, do not route signals with fast
transitions near MODESEL. This practice minimizes capacitive
coupling.
MUX/
TIMPRM
43
I
Multiplexed/Nonmultiplexed Select Pin/
Transmit Impedance/Receive Impedance Match
MUX:
In host mode with a parallel port, this pin is used to select
multiplexed address and data operation or separate address and
data. When mux is a high, multiplexed address and data is used.
TIMPRM:
In hardware mode, this pin selects the internal transmit
termination impedance and receive impedance match for E1 mode
and T1/J1 mode.
0 → 75
Ω for E1 mode or 100Ω for T1 mode
1 → 120
Ω for E1 mode or 110Ω for J1 mode
Note: If the part number ends with 120, the default is 120
Ω when
low and 75
Ω when high for El mode only.
MOTEL/
CODE
88
I
Motorola Intel Select/Code
MOTEL:
When in parallel host mode, this pin selects Motorola
mode when low and Intel mode when high.
CODE:
In hardware mode, AMI encoding/decoding for all the LIUs
is selected when the pin is high. When the pin is low, B8ZS is
selected for T1 mode and HDB3 for E1 mode for all the LIUs.
CSB/
JAS
87
I
(In HW
mode,
pulled
to
VDDIO/2)
Chip Select Bar/Jitter Attenuator Select
CSB:
This signal must be low during all accesses to the registers.
JAS:
In hardware mode, this pin is used as a jitter attenuator
select.
Low → Jitter attenuator is in the transmit path.
VDDIO/2 → Jitter attenuator is not used.
High → Jitter attenuator is in the receive path.
Note: When left unconnected in hardware mode, do not route
signals with fast transitions near JAS, in order to minimize
capacitive coupling.
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