參數(shù)資料
型號: DS2490S
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Bus Controller
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO24
封裝: 0.300 INCH, SO-24
文件頁數(shù): 49/51頁
文件大?。?/td> 444K
代理商: DS2490S
DS2490
7 of 50
DS2490 will then wait for tFILL to expire and then, depending on the value of embedded 1-WIRE RESET
command bits PST, NTF, and ICP, generate a command response byte that is available to the host.
If the test for interrupt or short reveals a logic 0, the DS2490 will wait for 4096s and then test the 1-
Wire bus again. If a logic 0 is detected, the 1-Wire bus is shorted and the DS2490 feedback response for
the 1-WIRE RESET communication command will indicate a short detection. If a logic 1 is detected, the
device will wait for tFILL to expire, after which it will load the feedback response value for the 1-WIRE
RESET command with an alarming presence pulse detect value. See the DEVICE FEEDBACK section
for additional details. No additional testing for a presence pulse will be done. The DS2490 will perform
the short/interrupt testing as described also at overdrive speed, although interrupt signaling is only
defined for regular speed.
As shown in Figure 6, a Write-1 and Read Data time slot is comprised of the segments tLOW1, tDSO, and
tHIGH. During Write-1 time slots, after the Write-1 low time (tLOW1) expires, the DS2490 waits for the
duration of the data sample offset and then samples the 1-Wire voltage to read the response. After this,
the waiting time tHIGH1 must expire before the time slot is complete. As shown in Figure 7, a Write-0 time
slot consists of the two segments tLOW0 and tREC0.
If the network is large or heavily loaded, flexible speed should be selected and the Write-1 low time
(tLOW1) should be extended to more than 8s to allow the 1-Wire bus to completely discharge. Since a
large or heavily loaded network needs more time to recharge, it is also recommended to delay sampling
the bus for reading. A higher Data Sample Offset value (tDSO) will increase the voltage margin and also
provide extra energy to the slave devices when generating a long series of Write-0 time slots. However,
the total of tLOW1 + tDSO should not exceed 22s. Otherwise, the slave device responding may have
stopped pulling the bus low when transmitting a logic 0.
WRITE 1 AND READ DATA TIME SLOT Figure 6
NOMINAL TIMING VALUES
SPEED
t
LOW1
t
DSO
t
HIGH1
t
SLOT
REGULAR
8s
6s
54s
68s
OVERDRIVE
1s
8s
10s
FLEXIBLE*
8s to 15s
3s to 10s 54s
65s to 79s
*Powerup defaults for Flexible speed: t
LOW1
= 12s, t
DSO
= 7s
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