參數(shù)資料
型號(hào)： DS2433Y
英文描述： 4k-Bit 1-Wire EEPROM
中文描述： 4K的位的1 - Wire的EEPROM
文件頁(yè)數(shù)： 15/19頁(yè)
文件大?。?/td> 588K
代理商： DS2433Y
DS2433
15 of 19
1-WIRE SIGNALING
The DS2433 requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals except Presence Pulse are initiated by the bus master. The DS2433 can
communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the
overdrive mode, the DS2433 will communicate at regular speed. While in Overdrive Mode the fast
timing applies to all wave forms.
The initialization sequence required to begin any communication with the DS2433 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2433 is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a Reset
Pulse (t
RSTL
, minimum 480
μ
s at regular speed, 48
μ
s at Overdrive Speed). The bus master then releases
the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS2433 waits (t
PDH
, 15-60
μ
s at regular speed, 2-6
μ
s
at Overdrive speed) and then transmits the Presence Pulse (t
PDL
, 60-240
μ
s at regular speed, 8-24
μ
s at
Overdrive Speed).
A Reset Pulse of 480
μ
s or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS2433 is in Overdrive Mode and the Reset Pulse is no longer than 80
μ
s the device will remain in
Overdrive Mode.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2433 to the master
by triggering a delay circuit in the DS2433. During write time slots, the delay circuit determines when
the DS2433 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay
circuit determines how long the DS2433 will hold the data line low overriding the 1 generated by the
master. If the data bit is a “1”, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES
Figure 10
*In order not to mask interrupt signalling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always be less than 960 μs.
** Includes recovery time.
相關(guān)PDF資料
PDF描述
DS2434 Battery Identification Chip
DS2435 Battery Identification Chip with Time/Temperature Histogram
DS2436 Battery ID/Monitor Chip
DS2436Z Battery ID/Monitor Chip
DS2437S IC-SM-BATT MONITOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2433Y-Z01 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:4K-Bit 1-Wire EEPROM
DS2433Y-Z01/T&R 制造商:Maxim Integrated Products 功能描述:IC EEPROM 4KBIT 8SOIC
DS2433Y-Z01/T&R 功能描述:IC EEPROM 4KBIT 8SOIC RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線(xiàn)串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
DS2433-Z01 功能描述:IC EEPROM 4KBIT TO92-3 RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線(xiàn)串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
DS2434 功能描述:電池管理 RoHS:否 制造商:Texas Instruments 電池類(lèi)型:Li-Ion 輸出電壓:5 V 輸出電流:4.5 A 工作電源電壓:3.9 V to 17 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:VQFN-24 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*