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參數(shù)資料
| 型號(hào)： | DS2417P+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMECHIP W/INTRPT 1WIRE 6TSOC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類(lèi)型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 唯一 ID |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | 1 線 串行 |
| 電源電壓： | 2.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 6-LSOJ |
| 供應(yīng)商設(shè)備封裝： | 6-TSOC |
| 包裝： | 帶卷 (TR) |
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DS2417
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VPUP = external pullup voltage.
4. Input load is to ground.
5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1 s of this falling edge.
6. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always
guarantee a presence pulse.
7. The reset low time (tRSTL) should be restricted to a maximum of 960s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
8. When VDD ramps up, the oscillator is always off.
9. At VDD = 3V ± 10%
10. At VDD = 5V ± 10%
11.
VIH1 has to be VDD – 0.3V or higher.
12. The optimal sampling point for the master is as close as possible to the end time of the 15μs tRDV
period without exceeding tRDV. For the case of a Read-One Time Slot, this maximizes the amount of
time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a
read will occur before the fastest 1-Wire device(s) release the line.
13. The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
6 TSOC
D6+1
6 Flip Chip
BF611-2
15
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
2007 Maxim Integrated
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
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|---|---|
| DS2417V | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:1-Wire Time Chip With Interrupt |
| DS2417X | 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS2417X/T&R | 制造商:Maxim Integrated Products 功能描述:IC TIMECHIP W/INTRPT 1WIRE CSP |
| DS2417X/T&R | 功能描述:IC TIMECHIP W/INTRPT 1WIRE CSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| DS2421FP000 | 制造商:Thomas & Betts 功能描述:200A,CON,3P4W,MG,421,3P440V |
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