P3.6/
參數(shù)資料
型號: DS2251T-32-16#
廠商: Maxim Integrated Products
文件頁數(shù): 18/22頁
文件大?。?/td> 0K
描述: IC MCU 32KB 16MHZ 72-SIMM
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: DS225x
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: SIO,UART/USART
外圍設(shè)備: 電源故障復位,WDT
輸入/輸出數(shù): 32
程序存儲器類型: SRAM
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 72-SIMM
包裝: 托盤
DS2251T
5 of 22
PIN
DESCRIPTION
15
P3.5/T1. General-purpose I/O port pin 3.5. Also serves as the Timer 1 input.
16
P3.6/ WR . General-purpose I/O port pin. Also serves as the write strobe for Expanded bus
operation.
17
P3.7/ RD . General-purpose I/O port pin. Also serves as the read strobe for Expanded bus
operation.
9
RST. Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit
is not needed and is NOT recommended.
29
PSEN
. Program Store Enable. This active low signal is used to enable an external program
memory when using the Expanded bus. It is normally an output and should be unconnected
if not used.
30
ALE. Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent
latch.
19, 18
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
20
GND. Logic ground.
40
VCC. +5V
72
BA15. Monitor test point to reflect the logical value of A15. Not needed for memory access.
54–41
BA13–BA 0. Byte-wide Address bus bits 13–0. This bus is combined with the non-
multiplexed data bus (BD7–BD0) to access onboard NV SRAM and off-board peripherals.
Peripheral decoding is performed using PE3 and PE4 . These are on 16k boundaries, so
BA14 or BA15 are not needed. Read/write access is controlled by R/ W . BA13–BA0 connect
directly to memory-mapped peripherals.
63–56
BD7–BD0. Byte-wide Data Bus Bits 7–0. This 8-bit bi-directional bus is combined with the
non-multiplexed address bus (BA14–BA0) to access on-board NV SRAM and off-board
peripherals.
64
R/ W . Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
bus. It is controlled by the memory map and Partition. The blocks selected as Program
(ROM) will be write-protected. This signal is also used for the write enable to off-board
peripherals.
66
PE3
. Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any
type of peripheral function.
67
PE4
. Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any
type of peripheral function.
31
PROG
. Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading
on power-up. This signal is pulled up internally.
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