
DS21Q55 Quad T1/E1/J1 Transceiver 
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TABLE OF TABLES 
Table 2-A. Pin Description Sorted by Pin Number .....................................................................................................29 
Table 3-A. Register Map Sorted by Address..............................................................................................................36 
Table 7-A. T1 Alarm Criteria.......................................................................................................................................58 
Table 8-A. E1 Sync/Resync Criteria...........................................................................................................................60 
Table 8-B. E1 Alarm Criteria.......................................................................................................................................65 
Table 12-A. T1 Line Code Violation Counting Options...............................................................................................80 
Table 12-B. E1 Line-Code Violation Counting Options ..............................................................................................80 
Table 12-C. T1 Path Code Violation Counting Arrangements....................................................................................82 
Table 12-D. T1 Frames Out-of-Sync Counting Arrangements...................................................................................83 
Table 14-A. Time Slot Numbering Schemes..............................................................................................................94 
Table 15-A. Idle-Code Array Address Mapping........................................................................................................100 
Table 15-B. GRIC and GTIC Functions....................................................................................................................102 
Table 17-A. Elastic Store Delay After Initialization...................................................................................................112 
Table 21-A. HDLC Controller Registers ...................................................................................................................131 
Table 22-A. Transformer Specifications ...................................................................................................................162 
Table 25-A. Transmit Error-Insertion Setup Sequence ............................................................................................183 
Table 25-B. Error Insertion Examples ......................................................................................................................185 
Table 30-A. Instruction Codes for IEEE 1149.1 Architecture ...................................................................................202 
Table 30-B. ID Code Structure .................................................................................................................................203 
Table 30-C. Device ID Codes...................................................................................................................................203 
Table 30-D. Boundary Scan Control Bits..................................................................................................................204