參數(shù)資料
型號： DS21Q50LN
廠商： Maxim Integrated Products
文件頁數(shù)： 19/87頁
文件大?。?/td> 0K
描述： IC TRANSCEIVER E1 QD IND 100LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器
DS21Q50
26 of 87
Table 4-1. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and
N + 2, and FAS not present
in frame N + 1
Three consecutive incorrect FAS
received; Alternate (RCR1.2 = 1) the
above criteria is met or three consecutive
incorrect bit 2 of non-FAS received
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms
915 or more CRC4 codewords out of
1000 received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment word
found and previous time slot
16 contains code other than
all zeros
Two consecutive MF alignment words
received in error
G.732 5.2
Register Name:
TCR
Register Description:
Transmit Control Register
Register Address:
11 Hex
Bit
7
6
5
4
3
2
1
0
Name
IFSS
TFPT
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
NAME
BIT
FUNCTION
IFSS
7
Internal Frame Sync Select
0 = TSYNC normal
1 = If TSYNC is in the INPUT mode (TSIO = 0) then TSYNC is internally replaced by the
recovered receive frame sync. The TSYNC pin is ignored.
1 = If TSYNC is in the OUTPUT mode (TSIO = 1), TSYNC outputs the recovered
multiframe frame sync.
TFPT
6
Transmit Time Slot 0 Pass-Through
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
AEBE
5
Automatic E-Bit Enable
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
TUA1
4
Transmit Unframed All Ones
0 = transmit data normally
1 = transmit an unframed all-ones code
TSiS
3
Transmit International Bit Select
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, TCR.6 must be set to 0)
TSA1
2
Transmit Signaling All Ones
0 = normal operation
1 = force time slot 16 in every frame to all ones
TSM
1
TSYNC Mode Select
0 = frame mode (See the timing diagrams in Section 19.2.)
1 = CAS and CRC4 multiframe mode (See the timing diagrams in Section 19.2.)
TSIO
0
TSYNC I/O Select
0 = TSYNC is an input
1 = TSYNC is an output
Note: See Figure 19-9 for more details about how the transmit control register affects the operation of the DS21Q50.
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