參數(shù)資料
型號： DS21Q43AT
廠商： Maxim Integrated Products
文件頁數(shù)： 14/60頁
文件大?。?/td> 0K
描述： IC FRAMER E1 QUAD 5V IND 128TQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 72
控制器類型： E1 調(diào)幀器
接口： 并行/串行
電源電壓： 4.5 V ~ 5.5 V
電流 - 電源： 32mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
產(chǎn)品目錄頁面： 1429 (CN2011-ZH PDF)
21 of 60
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
LIRST
-
TBCS
-
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR3.7
Transmit Side Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
TCBFS
CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin.
1=TCBRs define which signaling bits are to be inserted.
TIRFS
CCR3.5
Transmit Idle Registers (TIR) Function Select.
0=TIRs define in which channels to insert idle code.
1=TIRs define in which channels to insert data from RSER.
ESR
CCR3.4
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. Should be toggled after
RSYSCLK and TSYSCLK have been applied and are stable.
Must be set and cleared again for a subsequent reset. Do not
leave this bit set high.
-
CCR3.3
Not Assigned. Should be set to 0 when written.
-
CCR3.2
Not Assigned. Should be set to 0 when written.
TBCS
CCR3.1
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
-
CCR3.0
Not Assigned. Should be set to 0 when written.
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS21Q43A should be configured for operation by writing
to all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR
bit should be toggled from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic store is not
being used).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS21Q43A,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q43AT+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43ATN 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad E1 Framer
DS21Q43-ATN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q44 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Enhanced QUAD E1 FRAMER
DS21Q44T 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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