參數(shù)資料
型號： DS21Q42T+
廠商： Maxim Integrated Products
文件頁數(shù)： 42/116頁
文件大?。?/td> 0K
描述： IC FRAMER ENHANCED T1 4X 128TQFP
標(biāo)準(zhǔn)包裝： 72
控制器類型： T1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-LQFP（14x20）
包裝： 管件
DS21Q42
31 of 116
CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex)
(MSB)
(LSB)
TESE
ODF
RSAO
TSCLKM
RSCLKM
RESE
PLB
FLB
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR1.7
Transmit Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
ODF
CCR1.6
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
RSAO
CCR1.5
Receive Signaling All One’s. This bit should not be enabled if
hardware signaling is being utilized. See Section 10 for more
details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKM
CCR1.4
TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSCLKM
CCR1.3
RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESE
CCR1.2
Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLB
CCR1.1
Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLB
CCR1.0
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
Payload Loopback
When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this
loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing
applications. In a PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs
corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6
calculation, and the FDL bits are not looped back, they are reinserted by the DS21Q42. When PLB is
enabled, the following will occur:
1) Data will be transmitted from the TPOS and TNEG pins synchronous with RCLK instead of TCLK
2) All of the receive side signals will continue to operate normally.
3) The TCHCLK and TCHBLK signals are forced low.
4) Data at the TSER and TSIG pins is ignored.
5) The TLCLK signal will become synchronous with RCLK instead of TCLK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q42T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q42TN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43A 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad E1 Framer
DS21Q43AT 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43AT+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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