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參數(shù)資料
| 型號： | DS21FF44 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300 |
| 文件頁數(shù)： | 45/110頁 |
| 文件大?。?/td> | 526K |
| 代理商： | DS21FF44 |
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DS21FT44/DS21FF44
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TABLE OF CONTENTS
1. MULTI-CHIP MODULE (MCM) DESCRIPTION ........................................................................ 1
2. MCM LEAD DESCRIPTION ........................................................................................................... 7
3. DS21FF44 (Four x Four) PCB LAND PATTERNS ...................................................................... 15
4. DS21FT44 (Four x Three) PCB Land Pattern ............................................................................... 16
5. DS21Q42 DIE DESCRIPTION........................................................................................................ 17
6. DS21Q44 INTRODUCTION ........................................................................................................... 18
7. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................. 21
8. DS21Q44 REGISTER MAP............................................................................................................. 27
9. PARALLEL PORT........................................................................................................................... 32
10. CONTROL, ID AND TEST REGISTERS ..................................................................................... 32
11. STATUS AND INFORMATION REGISTERS............................................................................. 41
12. ERROR COUNT REGISTERS ....................................................................................................... 47
13. DS0 MONITORING FUNCTION................................................................................................... 49
14. SIGNALING OPERATION............................................................................................................. 52
14.1 PROCESSOR BASED SIGNALING ........................................................................................................... 52
14.2 HARDWARE BASED SIGNALING ............................................................................................................. 55
15. PER–CHANNEL CODE GENERATION AND LOOPBACK .................................................... 56
15.1 TRANSMIT SIDE CODE GENERATION .................................................................................................... 56
15.1.1
Simple Idle Code Insertion And Per–Channel Loopback ................................................................... 56
15.1.2
Per–Channel Code Insertion .............................................................................................................. 57
15.2 RECEIVE SIDE CODE GENERATION....................................................................................................... 58
16. CLOCK BLOCKING REGISTERS ............................................................................................... 59
17. ELASTIC STORES OPERATION ................................................................................................. 60
17.1 RECEIVE SIDE ........................................................................................................................................... 61
17.2 TRANSMIT SIDE ........................................................................................................................................ 61
18. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION...................................... 61
18.1 HARDWARE SCHEME............................................................................................................................... 61
18.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME ............................................................ 62
18.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ....................................................... 63
19. HDLC CONTROLLER FOR THE SA BITS OR DS0 ................................................................. 65
19.1 GENERAL OVERVIEW .............................................................................................................................. 65
19.2 HDLC STATUS REGISTERS ..................................................................................................................... 66
19.3 BASIC OPERATION DETAILS ................................................................................................................... 67
19.4 HDLC REGISTER DESCRIPTION ............................................................................................................. 68
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21FF44N | DATACOM, FRAMER, PBGA300 |
| DS21FT40N | DATACOM, FRAMER, PBGA300 |
| DS21FT40 | DATACOM, FRAMER, PBGA300 |
| DS21FT42 | DATACOM, FRAMER, PBGA300 |
| DS21FT42N | DATACOM, FRAMER, PBGA300 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FF44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT40 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Four x Three 12 Channel E1 Framer |
| DS21FT40N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21FT42 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT42N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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