參數(shù)資料
型號: DS21FF42
廠商: Maxim Integrated Products
文件頁數(shù): 47/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應商設備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
38 of 114
SYMBOL
POSITION
NAME AND DESCRIPTION
TESMDM
CCR3.0
Transmit Elastic Store Minimum Delay Mode. See
Section 17 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
PULSE DENSITY ENFORCER
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:
– No more than 15 consecutive zeros
– At least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
POSITION
NAME AND DESCRIPTION
RSRE
CCR4.7
Receive Side Signaling Re–Insertion Enable. See Section
14 for details.
0 = do not re-insert signaling bits into the data stream
presented at the RSER pin
1 = reinsert the signaling bits into data stream presented at
the RSER pin
RPCSI
CCR4.6
Receive Per–Channel Signaling Insert. See Section 14 for
more details.
0 = do not use RCHBLK to determine which channels should
have signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
RFSA1
CCR4.5
Receive Force Signaling All Ones. See Section 14 for more
details.
0 = do not force extracted robbed–bit signaling bit positions
to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFE
CCR4.4
Receive Freeze Enable. See Section 14 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and
RSER if CCR4.7 = 1).
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相關代理商/技術參數(shù)
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DS21FF42+ 功能描述:網絡控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FF42N 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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