參數(shù)資料
型號: DS2187
廠商: Maxim Integrated Products
文件頁數(shù): 4/10頁
文件大?。?/td> 0K
描述: IC RECEIVE LINE INTERFACE 18-DIP
標(biāo)準(zhǔn)包裝: 20
功能: 接收線路接口
接口: T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 18mA
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 18-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 18-PDIP
包裝: 管件
包括: AMI / B8ZS / HDB3 編碼信號解碼器
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2187
3 of 10
PIN DESCRIPTION Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1AVDD
-
Analog Positive Supply. 5.0 volts.
2
RAIS
I
Reset Alarm Indication Signal.
Every other low pulse at this input
establishes the AIS alarm detection period.
3
ZCSEN
I
0 Code Suppression Enable.
When high, incoming B8ZS (RCLKSEL=0)
or HDB3 (RCLKSEL=1) code words are replaced with all 0s at RPOS and
RNEG; when low, no code replacement occurs.
4LCAP
-
Loop Cap.
Part of internal loop filter; attach a 10 microfarad capacitor from
this pin to VSS.
5
RCLKSEL
I
Receive Clock Select.
Tie to VSS for 1.544 MHz (T1) applications, to VDD for
2.048 MHz (CEPT) applications.
6
7
RTIP
RRING
I
Receive Tip and Ring.
Connect to line transformer as shown in Figure 2.
8
LOCK
O
Frequency Lock.
High state indicates that internal circuitry is phase- and
frequency-locked to the incoming signal at RRING and RTIP.
9
AVSS
-
Analog Signal Ground.
0.0 volts.
10
DVSS
-
Digital Signal Ground.
0.0 volts.
11
RCLK
O
Receive Clock.
Extracted line rate clock.
12
13
RNEG
RPOS
O
Receive Data.
Extracted receive data; updated on rising edge of RCLK.
14
NC
-
No Connect.
Do not connect to this pin.
15
BPV
O
Bipolar Violation.
Transitions high for the full bit period when a bit in
violation appears at RPOS or RNEG; B8ZS code words are not accused when
ZCSEN=1. BPV not valid for RCLKSEL=1 and ZCSEN=1.
16
AIS
O
Alarm Indication Signal.
High when the received data stream has contained
less than three 0s during the last two periods of the RAIS signal.
17
RCL
O
Receive Carrier Loss.
High if 192 0s appear at RPOS and RNEG; reset on
next occurrence of a one.
18
DVDD
-
Digital Positive Supply.
5.0 volts
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