參數(shù)資料
型號(hào): DS2181AQN/T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/32頁(yè)
文件大小: 0K
描述: IC TXRX CEPT PRIM RATE IN 44PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2181A
12 of 32
FIXED FRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically initiate frame search whenever the frame
alignment word is received in error three consecutive times.
FIXED CAS MULTIFRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically initiate frame search whenever two consecutive
CAS multiframe alignment words are received in error.
FIXED CRC4 RESYNC CRITERIA
If CCR.1=1 or if the TEST pin is tied high, then the DS2181A will initiate the resync at the FAS level if
915 or more CRC4 words out of 1000 are received in error.
CAS SIGNALLING SOURCE
CAS applications sample signaling data at TSER when TCR.6 = 0; an on-chip data multiplexer accepts
channel-associated data input at TSD when TCR.6 = 1. The data multiplexer must be disabled (TCR.6 =
0) when the CCS mode is enabled (TCR.5 = 1).
TSD INPUT TIMING (TCR.6 = 1; TCR.5 = 0) Table 6
FRAME #
TIMESLOT SIGNALING
DATA SAMPLED AT TSD
017
1
1, 18
2
2, 19
3
3, 20
4
4, 21
5
5, 22
6
6, 23
7
7, 24
8
8, 25
9
9, 26
10
0, 27
11
11, 28
12
12, 29
13
13, 30
14
14, 31
15
NOTE:
1. A, B, C and D data is sampled on falling edges of TCLK during bit times 5, 6, 7 and 8 of timeslots
indicated.
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