參數(shù)資料
型號： DS2181AQ+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： IC TXRX CEPT PRIMARY RATE 44PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準包裝： 500
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： CEPT
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2181A
20 of 32
RSR: RECEIVE STATUS REGISTER Figure 18
(MSB)
(LSB)
RRA
RDMA
RSA1
RUA1
FSERR
MFSERR
RLOS
ECS
SYMBOL
POSITION
NAME AND DESCRIPTION
RRA
RSR.7
Receive Remote Alarm. Set when bit 3 of timeslot 0 in non-align
frames set for three consecutive non-align frames.
RDMA
RSR.6
Receive Distant Multiframe Alarm. Set when bit 6 of timeslot 16
in frame 0 is set for three consecutive multiframes.
RSA1
RSR.5
Receive Signaling All Ones. Set when the contents of timeslot 16
have been all 1's for two consecutive frames.
RUA1
RSR.4
Receive Unframed All Ones. Set when less than three 0s have
been received in the last two consecutive frames.
FSERR
RSR.3
Frame Resync Criteria Met. Set when the frame error criteria are
met; also the frame resync is initiated if RCR.1=0.
MFSERR
RSR.2
CAS Multiframe Resync Criteria Met. Set when the CAS
multiframe error criteria are met; also, the frame resync is initiated
if RCR.1=0.
RLOS
RSR.1
Receive Loss of Sync. Set when resync is in progress.
ECS
RSR.0
Error Counter Saturation. Set when any of the on-chip counters
at FECR, CECR or BVCR saturates.
NOTE:
1. When in the CCS mode, the RDMA flag bit and the RDMA pin have no significance. It will be set
when bit 6 of timeslot 16 in frame 0 is set for three consecutive multiframes in either CAS or CCS
mode.
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