1 VALID DURING TIMESLOT # 0 15, -2 1
參數(shù)資料
型號: DS2181AN
廠商: Maxim Integrated Products
文件頁數(shù): 9/32頁
文件大?。?/td> 0K
描述: IC TXRX CEPT PRIM RATE IND 40DIP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 10
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: CEPT
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
DS2181A
17 of 32
RECEIVE SIGNALING Table 7
FRAME #
RSD
1 VALID DURING
TIMESLOT #
0
15,
-2
1
-2, 17
2
1, 18
3
2, 19
4
3, 20
5
4, 21
6
5, 22
7
6, 23
8
7, 24
9
8, 25
10
9, 26
11
10, 27
12
11, 28
13
12, 29
14
13, 30
15
14, 31
NOTES: (Applicable only to CAS systems)
1. RSD is valid for the least significant nibble in each indicated timeslot. Timeslot A data appears in bit
5, B in bit 6, C in bit 7 and D in bit 8.
2. RSD does not output valid data during timeslots 0 and 16.
RECEIVE MULTIFRAME TIMING Figure 15
RECEIVE TIMING
The receive side output timing set is identical to that found on the transmit side. The user can tie receive
outputs directly to the transmit inputs for drop and insert applications. The received data of RPOS, RNEG
appear at RSER after six RCLK delays, without any change except for the HDB3-to-NRZ conversion
when HDB3 is enabled.
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