參數(shù)資料
型號: DS21600SN
廠商: DALLAS SEMICONDUCTOR
元件分類: Clock Driver
英文描述: PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: SOIC-16
文件頁數(shù): 4/17頁
文件大小: 813K
代理商: DS21600SN
MAX4012/MAX4016/MAX4018/MAX4020
To implement the mux function, the outputs of multiple
amplifiers can be tied together, and only the amplifier
with the selected input will be enabled. All of the other
amplifiers will be placed in the low-power shutdown
mode, with their high output impedance presenting
very little load to the active amplifier output. For gains
of +2 or greater, the feedback network impedance of
all the amplifiers used in a mux application must be
considered when calculating the total load on the
active amplifier output
Output Capacitive Loading and Stability
The MAX4012/MAX4016/MAX4018/MAX4020 are opti-
mized for AC performance. They are not designed to
drive highly reactive loads, which decreases phase
margin and may produce excessive ringing and oscilla-
tion. Figure 5 shows a circuit that eliminates this prob-
lem. Figure 6 is a graph of the optimal isolation resistor
(RS) vs. capacitive load. Figure 7 shows how a capaci-
tive load causes excessive peaking of the amplifier’s
frequency response if the capacitor is not isolated from
the amplifier by a resistor. A small isolation resistor
(usually 20
to 30) placed before the reactive load
prevents ringing and oscillation. At higher capacitive
loads, AC performance is controlled by the interaction
of the load capacitance and the isolation resistor.
Figure 8 shows the effect of a 27
isolation resistor on
closed-loop response.
Coaxial cable and other transmission lines are easily
driven when properly terminated at both ends with their
characteristic impedance. Driving back-terminated
transmission lines essentially eliminates the line’s
capacitance.
Low-Cost, High-Speed, Single-Supply
Op Amps with Rail-to-Rail Outputs
12
______________________________________________________________________________________
OUT
IN-
EN_
IN+
10k
ENABLE
MAX40_ _
20
-160
050 100 150
300 350
500
-100
-120
0
mV ABOVE VEE
INPUT
CURRENT
(
A)
200 250
400 450
-60
-140
-20
-40
-80
0
-10
050 100 150
300 350
500
-7
-8
-1
mV ABOVE VEE
INPUT
CURRENT
(
A)
200 250
400 450
-3
-5
-9
-2
-4
-6
Figure 2. Enable Logic-Low Input Current vs. VIL
Figure 4. Enable Logic-Low Input Current vs. VIL with 10k
Series Resistor
Figure 3. Circuit to Reduce Enable Logic-Low Input Current
相關(guān)PDF資料
PDF描述
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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DS21602SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21604N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21600SN/T&R 制造商:Maxim Integrated Products 功能描述:DS21600SN SOIC IND T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC CLOCK RATE ADAPTER 16SOIC 制造商:Maxim Integrated Products 功能描述:Clock Generators & Support Products 3.3/5V Clock Rate Adapter
DS21600SN/T&R 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3/5V Clock Rate Adapter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
DS21600SN+ 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3/5V Clock Rate Adapter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
DS21600SN+T&R 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:CLOCK RATE ADPTR 16SOIC W - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC ADAPT CLK RATE 3.3V/5V 16SOIC 制造商:Maxim Integrated Products 功能描述:Clock Generators & Support Products 3.3/5V Clock Rate Adapter
DS21600SN+T&R 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3/5V Clock Rate Adapter RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56