參數(shù)資料
型號: DS21552L
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 6/139頁
文件大?。?/td> 1208K
代理商: DS21552L
DS21352/DS21552
103 of 137
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 19-2. Table 19-3 lists the device ID codes for the
SCT devices.
Table 19-2 ID CODE STRUCTURE
MSB
LSB
Version
Contact Factory
Device ID
JEDEC
1
4 bits
16bits
00010100001
1
Table 19-3 DEVICE ID CODES
DEVICE
16-BIT ID
DS21354
0005h
DS21554
0003h
DS21352
0004h
DS21552
0002h
19.4 TEST REGISTERS
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21352/552 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
BOUNDARY SCAN REGISTER
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 19-4 for all of the cell bit locations and definitions.
BYPASS REGISTER
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions which provides a short path between JTDI and JTDO.
相關(guān)PDF資料
PDF描述
DS21552LN DATACOM, PCM TRANSCEIVER, PQFP100
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